Abstract
Global register allocation is one of the most important optimizations in a compiler. Since the early 80’s, register allocation by graph coloring has been the dominant approach. The traditional formulation of graph-coloring register allocation implicitly assumes a single bank of non-overlapping general-purpose registers and does not handle irregular architectural features like overlapping register pairs, special purpose registers, and multiple register banks. We present a generalization of graph-coloring register allocation that can handle all such irregularities. The algorithm is parameterized on a formal target description, allowing fully automatic retargeting. We report on experiments conducted with a prototype implementation in a framework based on a commercial compiler.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
Hennessy, J.L., Patterson, D.A.: Computer Architecture: A Quantitative Approach, 2nd edn. Morgan Kaufmann Publishers, San Francisco (1996)
Chaitin, G.J., Auslander, M.A., Chandra, A.K., Cocke, J., Hopkins, M.E., Markstein, P.W.: Register allocation via coloring. Computer Languages 6, 47–57 (1981)
Appel, A.W.: Modern Compiler Implementation in ML. Cambridge University Press, Cambridge (1998)
Morgan, R.: Building an Optimizing Compiler. Digital Press (1998)
Muchnick, S.S.: Advanced Compiler Design and Implementation. Morgan Kaufmann, San Francisco (1997)
Briggs, P.: Register allocation via graph coloring. PhD thesis, Rice University (1992)
George, L., Appel, A.W.: Iterated register coalescing. In: TOPLAS, vol. 18, pp. 300–324 (1996)
Runeson, J., Nyström, S.O.: Generalizing Chaitin’s algorithm: Graph-coloring register allocation for irregular architectures. Technical Report 021, Departmentof Information Technology, Uppsala University, Sweden (2002)
Ramsey, N., Davidson, J.W.: Machine descriptions to build tools for embedded systems. In: Müller, F., Bestavros, A. (eds.) LCTES 1998. LNCS, vol. 1474, pp. 176–188. Springer, Heidelberg (1998)
Bradlee, D.G., Henry, R.R., Eggers, S.J.: The Marion system for retargetable instruction scheduling. In: PLDI (1991)
IAR Systems: EWARM (2003), http://www.iar.com/Products/?name=EWARM
Jagger, D., Seal, D.: ARM Architecture Reference Manual, 2nd edn. Addison-Wesley, Reading (2000)
Fraser, C.W., Hanson, D.R.: Simple register spilling in a retargetable compiler. Software - Practice and Experience 22, 85–99 (1992)
Guthaus, M.R., Ringenberg, J.S., Ernst, D., Austin, T.M., Mudge, T., Brown, R.B.: MiBench: A free, commercially representative embedded benchmark suite. In: IEEE 4th Annual Workshop on Workload Characterization (2001)
Engblom, J.: Why SpecInt95 should not be used to benchmark embedded systemstools. In: LCTES. ACM Press, New York (1999)
Smith, M.D., Holloway, G.: Graph-coloring register allocation for architectures with irregular register resources. (unpublished manuscript) (2001), http://www.eecs.harvard.edu/machsuif/publications/publications.html
Scholz, B., Eckstein, E.: Register allocation for irregular architectures. In: LCTES-SCOPES. ACM Press, New York (2002)
Kong, T., Wilken, K.D.: Precise register allocation for irregular register architectures. In: Proc. Int’l Symp. on Microarchitecture (1998)
Appel, A.W., George, L.: Optimal spilling for CISC machines with few registers. In: PLDI (2001)
Marwedel, P., Goosens, G.: Code Generation for Embedded Processors. Kluwer, Dordrecht (1995)
Bashford, S., Leupers, R.: Phase-coupled mapping of data flow graphs to irregular data paths. In: Design Automation for Embedded Systems, vol. 4, pp. 1–50. Kluwer Academic Publishers, Dordrecht (1999)
Kessler, C., Bednarski, A.: Optimal integrated code generation for clustered VLIW architectures. In: LCTES, pp. 102–111. ACM Press, New York (2002)
Author information
Authors and Affiliations
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2003 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Runeson, J., Nyström, SO. (2003). Retargetable Graph-Coloring Register Allocation for Irregular Architectures. In: Krall, A. (eds) Software and Compilers for Embedded Systems. SCOPES 2003. Lecture Notes in Computer Science, vol 2826. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39920-9_17
Download citation
DOI: https://doi.org/10.1007/978-3-540-39920-9_17
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-20145-8
Online ISBN: 978-3-540-39920-9
eBook Packages: Springer Book Archive