Abstract
Artificial neural networks can solve complex problems such as time series prediction, handwritten pattern recognition or speech processing. Though software simulations are essential when one sets about to study a new algorithm, they cannot always fulfill real-time criteria required by some practical applications. Consequently, hardware implementations are of crucial import.
The appearance of fast reconfigurable FPGA circuits brings about new paths for the design of neuroprocessors. A learning algorithm is divided into different steps that are associated with specific FPGA configurations. The training process then consists of alternating computing and reconfiguration stages. Such a method leads to an optimal use of hard-ware resources.
This paradigm is applied to the design of a neuroprocessor implementing multilayer perceptrons with on-chip training and pruning. All arithmetic operations are carried out with on-line operators. We also describe the principles of the hardware architecture, focusing in particular on the pruning mechanisms.
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Beuchat, JL., Sanchez, E. (1999). Using on-line arithmetic and reconfiguration for neuroprocessor implementation. In: Mira, J., Sánchez-Andrés, J.V. (eds) Engineering Applications of Bio-Inspired Artificial Neural Networks. IWANN 1999. Lecture Notes in Computer Science, vol 1607. Springer, Berlin, Heidelberg . https://doi.org/10.1007/BFb0100479
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DOI: https://doi.org/10.1007/BFb0100479
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