Abstract
In the current scenario, low power circuits can be designed using the concept of reversible logic. Here in this paper, reversible logic-based digital circuit like full adder is presented. The full adder circuit is implemented by using CMOS BSIM4 model. Design of reversible logic-based full adder circuit is efficient by considering various factors like the number of gates required, quantum cost, number of garbage outputs, and constant inputs. The reversible logic-based design is implemented and simulated with the help of tanner EDA tool having a version of tanner 13.0 tools. It has some performance parameter which is compulsorily considered for the completion of reversible logic circuit. System ideas of reversible logic circuits are cryptography, digital signal processing, computer graphics, and network congestion.
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Horke, S., Waje, M., Patil, R. (2020). Performance Analysis of Reversible Logic-Based Full Adder Using BSIM4 Model. In: Iyer, B., Deshpande, P., Sharma, S., Shiurkar, U. (eds) Computing in Engineering and Technology. Advances in Intelligent Systems and Computing, vol 1025. Springer, Singapore. https://doi.org/10.1007/978-981-32-9515-5_62
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DOI: https://doi.org/10.1007/978-981-32-9515-5_62
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Publisher Name: Springer, Singapore
Print ISBN: 978-981-32-9514-8
Online ISBN: 978-981-32-9515-5
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