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Part of the book series: Algorithms for Intelligent Systems ((AIS))

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Abstract

This paper presents a low-power voltage-controlled ring oscillator (VCO) designed using TSMC 0.18 μm CMOS technology. A resistive-capacitive tuning method is adopted to achieve a variable frequency in the proposed VCO design. The results show that the proposed VCO oscillates from 0.593 to 1.557 GHz by changing drain/source voltage (Vds) and gate voltage (Vg) from 1 to 1.8 V at fixed 1.8 V supply voltage (Vdd) with variable MOS varactor width (W). The proposed VCO achieves −96.557 dBc/Hz phase noise at 1 MHz offset from 1.386 GHz oscillation frequency while having 0.461 mW power dissipation in the circuit at 1.8 V (Vdd). The proposed VCO circuit shows a figure of merit (FoM) of 162.75 dBc/Hz at 1 MHz.

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Dwivedi, D., Kumar, M. (2022). An Improved CMOS Ring VCO Design with Resistive-Capacitive Tuning Method. In: Dua, M., Jain, A.K., Yadav, A., Kumar, N., Siarry, P. (eds) Proceedings of the International Conference on Paradigms of Communication, Computing and Data Sciences. Algorithms for Intelligent Systems. Springer, Singapore. https://doi.org/10.1007/978-981-16-5747-4_4

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