Abstract
In this paper, carry-skip adder is implemented using carry-select modified-tree (CSMT) adder and parallel prefix adder (PPA) topologies. This implementation is suitable for low-power application. The CSMT adder is designed using multiplexers. This adder uses very few numbers of multiplexers in their design, thereby low power can be achieved. PPA structure decreases number of stages in the design as well as smaller delays. The results of the implementation are compared with the conventional method in terms of power, delay and number of gates.
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Sridevi Sathya Priya, S., Poulraju, B., Benita, B., Karanatakam, D. (2020). Efficient Implementation of Carry-Skip Adder Using CSMT Adder and PPA. In: Tuba, M., Akashe, S., Joshi, A. (eds) Information and Communication Technology for Sustainable Development. Advances in Intelligent Systems and Computing, vol 933. Springer, Singapore. https://doi.org/10.1007/978-981-13-7166-0_29
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DOI: https://doi.org/10.1007/978-981-13-7166-0_29
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