Keywords

1 Introduction

The demand of bandwidth for the transmission has increased a lot with the rapidly development of integrated circuit, which caused interface bandwidth become a bottleneck for performance improvement in digital systems [1]. Traditional parallel interface need more chip pins to provide enough bandwidth but its signal attenuation also become a serious problem while data rate beyond 1 Gbps [8]. However, high-speed serial link which based on SerDes (Serializer, De-serializer) can work at dozens of Gbps and consume less energy [3], such as PCIE and RapidIO, which attract many researchers interest. SerDes chips adopt analog and digital circuit mixed design technology to resolve signal integrality problems such as channel attenuation and Inter Symbol Interference (ISI)[10].

Transmitter is an important part in SerDes which consume a large percentage of serial-link power. Most transmitters adopt 2-tap pre-emphasis that data code and pre-emphasis code combine with voltage or current mode to form a pre-emphasis driver. Young-Hoon song and Samuel Palermo designed a voltage-mode transmitter with current-mode equalization in 90-nm CMOS baud rate achieving 6 Gbps [6], which makes full use of current mode pre-emphasis and low power consumption characteristics. Huang proposed a 80 mw 40 GB/s transmitter with automatic serializing time window search and 2-tap pre-emphasis in 65 nm CMOS technology [4], but it is not programmable. This paper proposes a programmable pre-emphasis transmitter for SerDes, which not only realizes traditional function of driver circuit, but also adds extensibility and programmable ability with little complexity. This transmitter realize programmable pre-emphasis and output amplitude based on 40 nm COMS process. Moreover, it can work in different channel conditions at 2.5–6.25 GB/s transmission rate, and satisfying variety of standard protocols.

The paper is organized as follows: Sect. 2 explains the pre-emphasis technique and the overall architecture of the SerDes. The circuit design of functional blocks is described in Sect. 3. Section 4 shows the implementation and simulation results. Finally, a conclusion is made in Sect. 5.

2 Pre-emphasis Technique

An ideal rectangular wave can be decomposed into different frequency cosine harmonic [7], and the attenuation always occurs on high frequency due to the low pass characteristics of transmission channel. Moreover, the high frequency components mainly affect the signal jump edge, so compensating attenuation means compensating signal jump edge, i.e. pre-emphasis technique [5]. Figure 1 shows the pre-emphasis amplifies the high frequency components, which can offset emphasis and attenuation to obtain a smooth response [2].

The basic structure of the 2-tap pre-emphasis driver as shown in Fig. 2(a), imain and ipos are two tail currents Rt is a 50 \(\Omega \) resistor network to match channel impedance, and vptx is supply voltage. The serializer provides differential bits mainp/mainn and pre-emphasis bits pos1p/pos1n, and combining them in form of current or voltage to realize pre-emphasis.

Fig. 1.
figure 1

The function of pre-emphasis

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We list the voltages of txp, txn and their difference in Table 1, and the corresponding values of differential bits MAIN and pre-emphasis bits POS1 are list in Fig. 2(b).

Fig. 2.
figure 2

Two-tap current mode pre-emphasis driver. (a) is the driver circuit, (b) is the input data code

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Table 1. The output voltage of driver (Rt = 50 \(\Omega \))
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According to the Table 1, the output differential swing A1 and the differential swing A2 (without emphasis) is:

$$\begin{aligned} \mathrm {A1 = txp - txn = (imain + ipmos)*Rt} \end{aligned}$$
(1)
$$\begin{aligned} \mathrm {A2 = (imain - ipmos)*Rt} \end{aligned}$$
(2)

The pre-emphasis gain is:

(3)

When output swing A1, pre-emphasis gain and termination resistors Rt are fixed, the imain and ipos can be calculated base on (1) and (2):

$$\begin{aligned} \mathrm{{imain = 0}}\mathrm{{.5}}*\mathrm{{(1 + }}\frac{{A2}}{{A1}}\mathrm{{)}}*\frac{{A1}}{{Rt}} \end{aligned}$$
(4)
$$\begin{aligned} \mathrm{{ipos = 0}}\mathrm{{.5*(1 - }}\frac{{A2}}{{A1}}\mathrm{{)*}}\frac{{A1}}{{Rt}} \end{aligned}$$
(5)

3 Circuit Design

The overall structure of the proposed transmitter is shown in Fig. 3, which consists of synchronization module, serializer and driver.

Fig. 3.
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The overall structure of transmitter

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Synchronization module preprocesses the data which come from data link layer that transfer it into 20 bits. Then, choosing one in three base on the control bits, and the three choices include 20 bits parallel data, the output of PRBS generator, and Beacon code. This module can be realized by Verilog programming.

Serializer adopts multi-phase single-stage and single-phase multi-stage circuit to realize serialization, which can raise the clock frequency step by step and reduce this modules working at high frequency clock. 20 bits parallel data are serialized to 1 bit after three stage serialization in its correspond clock frequency.

The driver converts digital signal to analog signal and realizes pre-emphasis before signals are sent to the channel. The width of the final output waveform and swing are determined by driver when impedance is matched.

3.1 Serializer Circuit Design

The structure of serializer is shown in Fig. 4, serializer converts parallel data to serial bit through three stages. Firstly, the input parallel data (20 bits) are divided into four channels each is 5 bits, and then sent them into four identical 5:1 selectors respectively to obtain 4 bits parallel data. Secondly, the 4 bits data are divided into two groups: data_a/b and data_c/d, taking data_a/b as a example, let data_a and data_b align with the posedge and the negedge of the \(5^*\)ft clock respectively to obtain signal a/b. Then a/b are sent into 2:1 selector for the second serialization under the \(5^*\)ft clock (sa). The selector is static CMOS circuit, their signal processing obeys:

$$\begin{aligned} \mathrm{{out = }}\overline{\overline{sa \bullet a} \bullet \overline{sb \bullet b} } = sa \bullet a + sb \bullet b \end{aligned}$$
(6)
Fig. 4.
figure 4

The overall structure of transmitter

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By the way, the pre-emphasis data obtained by utilizing a latch delay a clock cycle for the output data of the second serialization.

The third serialization realizes 2:1 conversion for the data bit and pre-emphasis bit using two selectors under the 10 ft clock. The structure of the selector is the same as the second serialization. In Fig. 4, XX means a number of parallel identical selectors, because multiple parallel selectors can increase the current and make the serialization work faster [9].

3.2 Pre-emphasis Programmable Design

According to Eq. (3), the effect of pre-emphasis can be expressed as:

(7)

In order to realize programmable pre-emphasis, i.e. programmable ipos, this paper design current steering DAC circuit is shown in Fig. 5, in which iref is a reference current, tr_h[4:0] and tr_hn[4:0] are control bits, so ipos is determined by:

$$\begin{aligned} ipos = \sum \nolimits _{i = 0}^{i = 4} {tr} \_h[i] \bullet iref \end{aligned}$$
(8)
Fig. 5.
figure 5

Current tail DAC circuit

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Fig. 6.
figure 6

The overall structure of transmitter

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Speed requirement is not strict to this DAC [11], because of current ipos is fixed when control bits are configured. In this paper, in order to get an accurate and steady current, we adopt cascode source current.

3.3 Driver Circuit Design

Figure 6 illustrates three modules of the driver in this paper, the biasing module produces current imain with the reference of current iref, the lower part is pre-emphasis programmable circuit which produces ipos. Main module and pos module are current mode driver.

When tr_h[4:0] = 10001 and Rt = 50 \(\Omega \), the result of simulation is shown in Fig. 7(a). The serial data baud rate is 5 GB/s and the pre-emphasis gain (EQ) is about 2 dB. Figure 7(b) shows indicate that there is liner correlation between tr_h[4:0] and EQ.

Fig. 7.
figure 7

The simulation results of pre-emphasis. (a) tr_h[4:0] = 10001(Hspice) (b) Correlations between tr_h[4:0] and EQ

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4 Simulation Results

4.1 Simulation in Normal Transmission State

Figure 8 illustrates output waveforms and eye diagram in normal transmission state, we set tr[4:0] = 11011, common mode voltage is 1.2 V, EQ is 6 dB, and the output serial data baud rate is 6.25 Gbps.

Fig. 8.
figure 8

The output waveform and eye diagram of transmitter

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Table 2 lists the simulation result in different corner. Take TT as a example, the output differential swing is 979.35 mV, EQ is 6.08 dB, the rise and fall time is 68ps on average with 0.906-UI eye width, common mode voltage is 1.234 V. All the parameters meet the requirements of RapidIO 2.2 and PCIE 2.1. Because of the length of channel is short in short distance RapidIO2.2, pre-emphasis is unnecessary and need some extra simulation.

Table 2. The simulation result in normal transmission state
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Fig. 9.
figure 9

The wave and eye diagram of short-distance transmission (corner: TT)

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For the situation of short-distance transmission, The attenuation can be ignored due to the channel is short, so we set the control bits tr[4:0] = 0000 to close pre-emphasis and lower the signal swing to decrease power consumption. Figure 9 shows the simulation wave when the level[5:0] = 100011, the output wave swing is 0.55 V in this moment.

4.2 Simulation with Package

Figure 10 shows the simulation result when the pre-emphasis is 6 dB, common mode level is 1.2 V and the input data is PRBS7 code. The output signal differential swing of driver is about 1 V, and waveform becomes smooth through the channel due to the pre-emphasis offsets the decay of high frequency. The swing is reduced to approximately 0.6 V which is approximately equivalent to 10 dB attenuation.

Fig. 10.
figure 10

The overall structure of transmitter

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5 Conclusion

This paper proposes a transmitter based on 40 nm process, which can work at 2.5–6.25 GB/s data rate, offer 0–6 dB programmable pre-emphasis, common mode, and meeting PCIE2.1 and RapidIO2.2 protocols. By using simple DAC and amplifier, this design not only realizes traditional function of driver circuit, but also adds extensibility as well as programmable ability with little complexity which is the trend in multi-protocol supporting circuit design. The most difficult part of this design is that it needs more transistors due to the large total current of branches.