Basic Building Blocks

Abstract

 

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Digital circuits are no longer defined by logical schemes but by Hardware Description Language programs [1]. The translation of this kind of definition to an actual implementation is realized by Electronic Automation Design tools (Chap. 5). All along this book the chosen language is VHDL. In this chapter the most useful constructions are presented. For all of the proposed examples, the complete source code is available at the Authors’ web page.

1.1 Combinational Components

1.1.1 Boolean Equations

Among the predefined operations of any Hardware Description Language are the basic Boolean operations. Boolean functions can easily be defined. Obviously, all the classical logic gates can be defined. Some of them are considered in the following example.

Example 1.1

The following VHDL instructions define the logic gates NOT, AND2, OR2, NAND2, NOR2, XOR2, XNOR2, NAND3, NOR3, XOR3, XNOR3 (Fig. 1.1).

Fig. 1.1

Logic gates

The same basic Boolean operations can be used to define sets of logic gates working in parallel. As an example, assume that signals a = (a_n−1, a_n−2,…, a₀) and b = (b_n−1, b_n−2,…, b₀) are n-bit vectors. The following assignation defines a set of n AND2 gates that compute c = (a_n−1·b_n−1, a_n−2·b_n−2,…, a₀·b₀):

More complex Boolean functions can also be defined. It is worthwhile to indicate that within most Field Programmable Gate Arrays (FPGA) the basic combinational components are not 2-input logic gates but Look Up Tables (LUT) allowing the implementation of any Boolean function of a few numbers (4, 5, 6) of variables (Chap. 5). Hence, it makes sense to consider the possibility of defining small combinational components by the set of Boolean functions they implement.

Example 1.2

The following VHDL instruction defines an ANDORI gate (a 4-input 1-output component implementing the complement of a·b v c·d, Fig. 1.2) and the two following instructions define a 1-bit full adder (a 3-input 2-output component implementing a+b+c _in mod 2 and a·b v a·c _in v b·c _in , Fig. 1.3).

Fig. 1.2

ANDORI gate

Fig. 1.3

One-bit full adder

1.1.2 Tables

Combinational components can also be defined by their truth tables, without the necessity to translate their definition to Boolean equations. As a first example, consider a 1-digit to 7-segment decoder, that is a 4-input 7-output combinational circuit.

Example 1.3

The behavior of a 4-to-7 decoder (Fig. 1.4) can be described by a conditional assignment instruction

Fig. 1.4

Four-digit to seven-segment decoder

The last choice of a WITH… SELECT construction must be WHEN OTHERS in order to avoid the inference of an additional latch, and it is the same for other multiple choice instructions such as CASE.

As mentioned above, small Look Up Tables are basic components of most FPGA families. The following example is a generic 4-input 1-output LUT.

Example 1.4

The following entity defines a 4-input Boolean function whose truth vector is stored within a generic parameter (Fig. 1.5). Library declarations are omitted.

Fig. 1.5

Four-input Look Up Table

Then the following component instantiation defines a 4-input XOR function.

Comment 1.1

The VHDL model of the preceding Example 1.4 can be used for simulation purposes, independently of the chosen FPGA vendor. Nevertheless, in order to implement an actual circuit, the corresponding vendor’s primitive component should be used instead (Chap. 5).

1.1.3 Controllable Connections

Multiplexers are the basic components for implementing controllable connections. Conditional assignments are used for defining them. Some of them are considered in the following example.

Example 1.5

The following conditional assignments define a 2-to-1 and a 4-to-1 multiplexer (Fig. 1.6). The signal types must be compatible with the conditional assignments: a, b, c, d and e are assumed to be n-bit vectors for some constant value n.

Fig. 1.6

Multiplexers

Demultiplexers, address decoders and tri-state buffers are other components frequently used for implementing controllable connections such as buses.

Example 1.6

The following equations define a 1-bit 1-to-2 demultiplexer (Fig. 1.7a)

Fig. 1.7

Demultiplexers

and the following conditional assignments a 1-to-4 demultiplexer (Fig. 1.7b)

In the second case the signal types must be compatible with the conditional assignments: a, b, c, d and e are assumed to be n-bit vectors for some constant value n.

An address decoder is a particular case of 1-bit demultiplexer whose input is 1.

Example 1.7

The following equations define a 3-input address decoder (Fig. 1.8).

Fig. 1.8

Address decoder

Three-state buffers implement controllable switches.

Example 1.8

The following conditional assignment defines a tri-state buffer (Fig. 1.9): when the enable signal is equal to 1, output b is equal to input a, and when the enable signal is equal to 0, output b is disconnected (high impedance state). The signal types must be compatible with the conditional assignments: a and b are assumed to be n-bit vectors for some constant value n.

Fig. 1.9

Three-state buffer

An example of the use of demultiplexers and tri-state buffers, namely a data bus, is shown in Fig. 1.10.

Fig. 1.10

Example of a data bus

Example 1.9

The circuit of Fig. 1.10, made up of demultiplexers and three-state buffers, can be described by Boolean equations (the multiplexers) and conditional assignments (the three-sate buffers).

Nevertheless, the same functionality can be implemented by an 8-bit 5-to-1 multiplexer (Fig. 1.11).

Fig. 1.11

Data bus, second version

Generally, this second implementation is considered safer than the first one. In fact, tri-state buffers should not be used within the circuit core. They should only be used within I/O-port components (Sect. 1.4).

1.1.4 Arithmetic Circuits

Among the predefined operations of any Hardware Description Language there are also the basic arithmetic operations. The translation of this kind of description to actual implementations, using special purpose FPGA resources (carry logic, multiplier blocks), is realized by Electronic Automation Design tools (Chap. 5).

Example 1.10

The following arithmetic equation defines an adder mod 2ⁿ, being a, b and s n-bit vectors and c _IN an input carry (Fig. 1.12a).

Fig. 1.12

n-bit adders

By adding a most significant bit 0 to one (or both) of the n-bit operands a and b, an n-bit adder with output carry c _OUT can be defined (Fig. 1.12b). The internal signal sum is an (n+1)-bit vector.

The following arithmetic equation defines an n-bit by m-bit multiplier where a is an n-bit vector, b an m-bit vector and product an (n+m)-bit vector (Fig. 1.13).

Fig. 1.13

n-bit by m-bit multiplier

Comment 1.2

In most VHDL models available at the Authors’ web page, the type unsigned has been used, so that bit-vectors can be treated as natural numbers. In some cases, it could be better to use the signed type, for example when bit-vectors are interpreted as 2’s complement integers, and when magnitude comparisons or sign-bit extensions are performed.

1.2 Sequential Components

1.2.1 Flip-Flops

The basic sequential component is the D-flip-flop. In fact, several types of D-flip-flop can be considered: positive edge triggered, negative edge triggered, with asynchronous input(s) and with complemented output.

Example 1.11

The following component is a D-flip-flop triggered by the positive edge of clk (Fig. 1.14a),

Fig. 1.14

D flip-flops

while the following, which is controlled by the negative edge of clkb, has two asynchronous inputs clearb (active at low level) and preset (active at high level), having clearb priority, and has two complementary outputs q and qb (Fig. 1.14b).

Comment 1.3

The use of level-controlled, instead of edge-controlled, components is not recommendable. Nevertheless, if it were necessary, a D-latch could be modeled as follows:

where en is the enable signal and d the data input.

1.2.2 Registers

Registers are sets of D-flip-flops controlled by the same synchronization and control signals, and connected according to some regular scheme (parallel, left or right shift, bidirectional shift).

Example 1.12

The following component is a parallel register with ce (clock enable) input, triggered by the positive edge of clk (Fig. 1.15).

Fig. 1.15

Parallel register

As a second example (Fig. 1.16), the next component is a right shift register with parallel input (controlled by load) and serial input (controlled by shift).

Fig. 1.16

Right shift register

1.2.3 Counters

A combination of registers and arithmetic operations permits the definition of counters.

Example 1.13

This defines an up/down counter (Fig. 1.17) with control signals load (input parallel_in), count (update the state of the counter) and upb_down (0: count up, 1: count down).

Fig. 1.17

Up/down counter

The following component is a down counter (Fig. 1.18) with control signals load (input parallel_in) and count (update the state of the counter). An additional binary output equal_zero is raised when the state of the counter is zero (all 0’s vector).

Fig. 1.18

Down counter

1.2.4 Finite State Machines

Hardware Description Languages allow us to define finite state machines at an input/output behavioral level. The translation to an actual implementation including registers and combinational circuits—a classical problem of traditional switching theory—is realized by Electronic Automation Design tools (Chap. 5).

In a Moore machine, the output state only depends on the current internal state (Fig. 1.19) while in a Mealy machine the output state depends on both the input state and the current internal state (Fig. 1.20). Let t _SUinput be the maximum set up time of the input state with respect to the positive clock edge, t ₁ the maximum delay of the combinational block that computes the next internal state, and t ₂ the maximum delay of the combinational block that computes the output state. Then, in the case of a Moore machine, the following conditions must hold

Fig. 1.19

Moore machine

Fig. 1.20

Mealy machine

$$ t_{SUinput} + t_{1} < T_{CLK} \;{\text{and}}\;t_{2} < T_{CLK}, $$

(1.1)

and in the case of a Mealy machine

$$ t_{SUinput} + t_{1} < T_{CLK} \;{\text{and}}\;t_{SUinput} + t_{2}< T_{CLK} . $$

(1.2)

The set up and hold times of the register (Chap. 6) have not been taken into account.

Example 1.14

A Moore machine is shown in Fig. 1.21. It is the control unit of a programmable timer (Exercise 2.6.2). It has seven internal states, three binary input signals start, zero and reference, and two output signals operation (2 bits) and done. It can be described by the following processes.

Fig. 1.21

An example of a Moore machine

Example 1.15

Consider the Mealy machine of Table 1.1. It has four internal states, two binary inputs x ₁ and x ₀, and one binary output z. Assume that x ₀ and x ₁ are periodic, but out of phase, signals. Then the machine detects if x ₀ changes before x ₁ or if x ₁ changes before x ₀. In the first case the sequence of internal states is A B C D A B… and z = 0. In the second case the sequence is D C B A D C… and z = 1.

Table 1.1 A Mealy machine: next state/z

It can be described by the following processes.

1.3 Memory Blocks

With regards to memory blocks, a previous comment similar to Comment 1.1 must be outlined: VHDL models can be generated for simulation purposes; nevertheless, in order to implement an actual circuit, the corresponding vendor’s primitive component should be used instead (Chap. 5).

Example 1.16

The following entity defines a Read Only Memory storing 2ⁿ m-bit words. The stored data is defined by a generic parameter (Fig. 1.22). Library declarations are omitted.

Fig. 1.22

Read only memory

Then the following component instantiation defines a ROM storing 16 4-bit words, namely

Example 1.17

The following entity defines a synchronous Random Access Memory storing 2ⁿ m-bit words (Fig. 1.23). A write input enables the writing operation. Functionally, it is equivalent to a Register File made up of 2ⁿ m-bit registers whose clock enable inputs are connected to write, plus an address decoder. Library declarations are omitted.

Fig. 1.23

Random access memory

The following component instantiation defines a synchronous RAM storing 16 4-bit words.

1.4 IO-Port Components

Once again, a previous comment similar to Comment 1.1 must be outlined: VHDL models can be generated for simulating input and output amplifiers; nevertheless, in order to implement an actual circuit, the corresponding vendor’s I/O component should be used instead (Chap. 5).

In order to generate VHDL models of I/O amplifiers, it is convenient to understand the meaning of the STD_LOGIC type elements, that is

• ‘X’: forcing unknown, ‘0’ : forcing 0, ‘1’ : forcing 1,

• ‘W’: weak unknown, ‘L’ : weak 0, ‘H’ : weak 1,

• ‘Z’: high impedance

(“uninitialized” and “don’t care” states have no sense in the case of I/O amplifiers).

An amplifier generates low-impedance (forcing) signals when enabled and high impedance signals when disabled. Thus the possible outputs generated by an amplifier are ‘X’, ‘0’, ‘1’ and ‘Z’. In the following example several types of input, output and bidirectional amplifiers are defined.

Example 1.18

The following conditional assignment defines an input buffer (Fig. 1.24a):

Fig. 1.24

I/O ports

An input buffer with a pull-up resistor can be defined as follows (Fig. 1.24b).

The definition of a tri-state output buffer (Fig. 1.24c) is the same as in example 1.8, that is

An open-drain output can be defined as follows (Fig. 1.24d).

As an example of hierarchical description, a bidirectional I/O buffer can be defined by instantiating an input buffer and a tri-state output buffer (Fig. 1.24e).

1.5 VHDL Models

The following complete VHDL models are available at the Authors’ web page www.arithmetic-circuits.org:

• logic_gates.vhd (Sects. 1.1.1, 1.1.2 and 1.1.3),

• arithmetic_blocks.vhd (Sects. 1.1.4, 1.2.1 and 1.2.2),

• sequential_components.vhd (Sects. 1.2.1, 1.2.2 and 1.2.3),

• fnite_state_machines.vhd (Sect. 1.2.4),

• memories.vhd (Sect. 1.3),

• input_output.vhd (Sect. 1.4).

1.6 Exercises

 

• 1. Generate the VHDL model of a circuit that computes y = a·x where a is a bit, and x and y are n-bit vectors, so that y = (a·x _n−1, a·x _n−2,…, a·x ₀).

• 2. Generate several models of a 1-bit full subtractor (Boolean equations, table, LUT instantiation).

• 3. Generate a generic model of an n-bit 8-to-1 multiplexer.

• 4. Generate a generic model of an n-input address decoder.

• 5. Design an n-bit magnitude comparator: given two n-bit naturals a and b, it generates a 1-bit output gt equal to 1 if a ≥ b and equal to 0 if a < b.

• 6. Design a 60-state up counter with reset and count control inputs.

• 7. Design a finite state machine with two binary inputs x and y and a binary output z defined as follows: if the input sequence is (x, t) = 00 01 11 10 00 01 11… then z = 0, and if the input sequence is (x, y) = 00 10 11 01 00 10 11… then z = 1.