Summary
We present a new analytical performance model of the IEEE P1596 Standard Coherent Interface operating on the default unidirectional ring architecture. The performance metrics are derived from the equilibrium probability of a cache line being in a given state; these are found by solving a set of fixed point equations. From this we derive expressions for the message traffic emanating from each node and over the ring taking into account the relevant traffic priorities in SCI. Further analysis then yields the mean memory access time and processor utilisation. We demonstrate the application of the model by comparing the performance of two different node configurations.
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References
A.J. Field and P.G. Harrison. “An Analytical Model of the Standard Coherent Interface’ sCI’”, Internal Report, Department of Computing, Imperial College, 1995.
S. Gjessing, D.B. Gustavson, J.R. Goodman, D.V. James and E.H Kristiansen. “The SCI Cache Coherence Protocol”. In Scalable Shared Memory Multiprocessors, M. Dubois and S. Thakkar, eds., Kluwer academic Publishers, Norwell, Mass. 1992.
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S.L. Scott, J.R. Goodman and M.K. Vernon. “Performance of the SCI ring”, In Proc. of the 19th Annual Int. Sym. on Computer Architecture, May 1992.
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© 1995 ECSC-EC-EAEC, Brussels-Luxembourg
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Field, A.J., Harrison, P.G. (1995). A Fixed-Point Model of a Distributed Memory Consistency Protocol. In: Baccelli, F., Jean-Marie, A., Mitrani, I. (eds) Quantitative Methods in Parallel Systems. Esprit Basic Research Series. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-79917-4_16
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DOI: https://doi.org/10.1007/978-3-642-79917-4_16
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