Abstract
Pipelining computations over a large array of cells has been an important feature of systolic arrays. To achieve even higher degrees of concurrency, it is desirable to have cells of a systolic array themselves be pipelined as well. The resulting two-level pipelined systolic array would enjoy in principle a k-fold increase in its throughput, where k is the ratio of the time to perform the entire cell computation over that to perform just one of its pipeline stages. This paper describes such a two-level pipelined systolic array that is capable of performing convolutions of any dimension. The designs take full advantages of the pipelining assumed to be available at each cell.
Multi-stage pipelined arithmetic units built from discrete components have been used in most of high-performance computers. With the advent of VLSI, these pipelined units will surely be implemented in one or few chips. This paper shows for the first time how a large number of these pipelined chips can be efficiently combined to form a systolic array.
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References
H.T. Kung and C.E. Leiserson, “Systolic Arrays (for VLSI),” in I.S. Duff and G.W. Stewart (editors), Sparse Matrix Proceedings 1978, Society for Industrial and Applied Mathematics, pp.256–282,1979,
A sligtly different version appears in Introduction to VLSI Systems by C.A. Mead and L.A. Conway, Addison-Wesley, 1980, Section 8. 3.
H.T. Kung, “Why Systolic Architecture?” To appear in Computer, 1981.
H.T. Kung, “Special-Purpose Devices for Signal and Image Processing: An Opportunity in VLSI,” in Proceedings of the SPIE, Vol.241, Real-Time Signal Processing III, The Society of Photo-Optical Instrumentation Engineers, pp.76–84, July,1980.
H.T. Kung and S.W. Song, “A Systolic 2-D Convolution Chip,” Technical Report CMU-CS-81-110, Carnegie-Mellon University, Computer Science Department, March, 1981. Also to appear in Non-Conventional Computers and Image Processing: Algorithms and Programs, Leonard Uhr (editor), Academic Press, 1981.
D.W.L. Yen and A.V. Kulkarni, “The ESL Systolic Processor for Signal and Image Processing,” to appear in Proceedings of the 1981 IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, Hot Springs, Virginia, November 11–13, 1981.
L. Schirm IV, “Multiplier-Accumulator Application Notes,” TRW LSI Products, El Segundo, California, January, 1980.
H.T. Kung and R.L. Picard, “Hardware Pipelines for Multi-dimensional Convolution and Resampling,” to appear in Proceedings of the 1981 IEEE Computer Society Workshop on Computer Architecture for Pattern Analysis and Image Database Management, Hot Springs, Virginia, November 11–13, 1981.
TRW LSI Products, “TRW LSI Multipliers — HJ series,” TRW Inc., Redondo Beach, California, 1978.
L.M. Ruane, D.W.L. Yen, and H.T. Kung, “A Two-Level Pipelined Systolic Array for N-Dimensional Convolutions,” submitted to IEEE Transactions on Computers for publication.
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© 1981 Carnegie-Mellon University
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Kung, H.T., Ruane, L.M., Yen, D.W.L. (1981). A Two-Level Pipelined Systolic Array for Convolutions. In: Kung, H.T., Sproull, B., Steele, G. (eds) VLSI Systems and Computations. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-68402-9_28
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DOI: https://doi.org/10.1007/978-3-642-68402-9_28
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