Abstract
Due to the regularity of implementation, multiplexers are widely used in VLSI circuit synthesis. This paper proposes a technique for decomposing a function into 2-to-1 multiplexers performing area-power tradeoff. To the best of our knowledge this is the first ever effort to incorporate leakage into power calculation for multiplexer based decomposition. With respect to an initial ROBDD (Reduced Ordered Binary Decision Diagram) based representation of the function, the scheme shows more than 30% reduction in area, leakage and switching for the LGSynth91 benchmarks without performance degradation. It also enumerates the trade-offs present in the solution space for different weights associated with these three quantities.
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References
Akers, S.B.: Binary decision diagrams. IEEE Trans on Computers C-27(6), 509–516 (1978)
Thompson, Packan, P., Bohr, M.: MOS Scaling: Transistor Challenges for the 21st Century. Intel Technology Journal, Q3 (1998)
Narayanan, U., Leong, H.W., Chung, K., Liu, C.L.: Low Power Multiplexer Decomposition. In: International Symposium on Low Power Electronics and Design, pp. 269–274 (1997)
Thakur, S., Wong, D.F., Krishnamoorthy, S.: Delay Minimal Decomposition of Multiplexers in Technology Mapping. In: Design Automation Conference, pp. 254–257 (1996)
Murgai, R., Brayton, R.K., Sangiovanni- Vincentelli, A.: An improved Synthesis Algorithm for Multiplexer-based PGA’s. In: Design Automation Conference, pp. 404–410 (1995)
Rudell, R.: Logic Synthesis for VLSI Design, PhD Thesis, U.C. Berkley (April 1989)
Kim, K., Ahn, T., Han, S.Y., Kim, C.S., Kim, K.H.: Low-power multiplexer decomposition by suppressing propagation of signal transitions. In: IEEE International Symposium on Circuits and Systems, vol. 5, pp. 85–88 (2001)
Anis, M., Elmasry, M.: Multi-Threshold CMOS Digital Circuits Managing Leakage Power, p. 14. Kluwer academic publishers, Dordrecht (2003)
Roy, K., Mukhopadhyay, S., Mahmoodi-Meimand, H.: Leakage Current Mechanisms and Leakage Reduction Techniques in Deep-Submicrometer CMOS Circuits. Proceedings of the IEEE 91(2), 305–327 (2003)
Roy, K., Prasad, S.C.: Low-Power CMOS VLSI Circuit Design. John Wiley & Sons, Inc., Chichester (2000)
Lindgren, P., Kerttu, M., Thornton, M., Drechsler, R.: Low Power Optimization Technique for BDD Mapped Circuits. In: Asia South Pacific Design Automation Conference, pp. 615–621 (2001)
Satyanarayana, D., Chattopadhyay, S., Sasidhar, J.: Low Power Combinational Circuit Synthesis targeting Multiplexer based FPGAs. In: Proceedings of 17th International Conference on VLSI Design (2004)
BDD packages BuDDY, http://www.itu.dk/research/buddy
Computer-Aided benchmarking Laboratory, http://www.cbl.ncsu.edu/benchmarks
Lee, D., Blaauw, D., Sylvester, D.: Runtime Leakage Minimization through probability-Aware Dual Vt or Dual-Tox Assignment. In: Asia-Pacific Desig Automation Conference, pp. 399–404 (2005)
Paul, G., Pradhan, S.N., Bhattacharya, B.B., Pal, A., Das, A.: BDD-based synthesis of logic functions using adiabatic multiplexers. International Journal on Systemics, Cybernetics, and Informatics (IJSCI) 1, 44–49 (2006)
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Pradhan, S.N., Chattopadhyay, S. (2011). Multiplexer Based Circuit Synthesis with Area-Power Trade-Off. In: Meghanathan, N., Kaushik, B.K., Nagamalai, D. (eds) Advanced Computing. CCSIT 2011. Communications in Computer and Information Science, vol 133. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-642-17881-8_39
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DOI: https://doi.org/10.1007/978-3-642-17881-8_39
Publisher Name: Springer, Berlin, Heidelberg
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