Abstract
This work presents a new hardware acceleration solution for the H.264/AVC motion compensation process. A novel architecture is proposed to precede the luminance interpolation task, which responds by the highest computational complexity in the motion compensator. The accelerator module was integrated into the VHDL description of the MIPS Plasma processor, and its validation was accomplished by simulation. A performance comparison was made between a software implementation and a hardware accelerated one. This comparison indicates a reduction of 94% in processing time. The obtained throughput is enough to reach real time when decoding H.264/AVC Baseline Profile motion compensation for luminance at Level 3.
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Zatt, B., Ferreira, V., Agostini, L., Wagner, F.R., Susin, A., Bampi, S. (2007). Motion Compensation Hardware Accelerator Architecture for H.264/AVC. In: Mery, D., Rueda, L. (eds) Advances in Image and Video Technology. PSIVT 2007. Lecture Notes in Computer Science, vol 4872. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-77129-6_7
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DOI: https://doi.org/10.1007/978-3-540-77129-6_7
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