Abstract
This paper proposes a technique for extracting an instruction scheduler from a LISA processor description. The generated tool reads unscheduled, sequential assembly code from a C compiler. It schedules the instructions using an efficient backtracking scheduling algorithm that allows automated delay slot filling and utilization of instruction level parallelism. For an industrial network processor and a multimedia VLIW architecture the quality of the generated assembly code is compared to that of compilers with handwritten scheduler specifications.
This work has been partially supported by CoWare Inc.
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Wahlen, O. et al. (2003). Extraction of Efficient Instruction Schedulers from Cycle-True Processor Models. In: Krall, A. (eds) Software and Compilers for Embedded Systems. SCOPES 2003. Lecture Notes in Computer Science, vol 2826. Springer, Berlin, Heidelberg. https://doi.org/10.1007/978-3-540-39920-9_12
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DOI: https://doi.org/10.1007/978-3-540-39920-9_12
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