Voltage Regulators

Abstract

Compromises between speed and power are the new semiconductor reality of the twenty first century. To support the demand for decreasing cost per function, a focus on functional diversification, on-chip integration, parallelism, and dynamic control have been adopted, posing significant circuit and system level challenges on power delivery and management in modern ICs.

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Compromises between speed and power are the new semiconductor reality of the twenty first century. To support the demand for decreasing cost per function, a focus on functional diversification, on-chip integration, parallelism, and dynamic control have been adopted, posing significant circuit and system level challenges on power delivery and management in modern ICs. To cope with these challenges, traditional power delivery needs to be revised at the architectural, circuit, device, and material levels. Existing circuit level techniques to convert and regulate power are reviewed in this chapter in terms of the advantages, drawbacks, and compatibility, with a focus on on-chip integration of heterogeneous systems.

One of the basic building blocks of converting and regulating power within a power delivery system is a DC-DC power converter. Power supplies step voltage signals either up (boost) or down (buck) and supply the required current to the load, while regulating output voltages under PVT, line, and load variations. The power efficiency of the conversion process has historically been the defining characteristic of a power supply. With increasing on-chip noise and demand on the quality of the dynamically controlled power, load regulation of the power supply has also become critical. With on-chip integration, the physical area of these power supplies is an additional concern.

Two typical strategies to convert power are to utilize passive storage elements for energy conversion (switching topologies) or to dissipate the excess energy within a resistive element (linear topologies). Historically, large switching power supplies are preferred over compact linear power supplies due to the high, ideally 100 %, power efficiency of switching converters. With on-chip power converters, strict area constraints are imposed on the DC-DC converters, affecting the choice of power supply topology. Compact switching power converters can potentially be designed at higher switching frequencies. The parasitic impedance in these converters however increases, degrading the power efficiency of the power delivery system.

The delivery of high quality power to the on-chip circuitry with minimum energy loss is a fundamental requirement of all ICs. To supply sufficient power, a higher unregulated DC voltage is usually stepped down and regulated within the power delivery system [308]. Power conversion and regulation resources need to be efficiently managed to supply high quality power with minimum energy losses within multiple on-chip voltage domains [289]. The design complexity of a power delivery system increases with greater requirements on the quality of the power supply, limitations of the passive elements, board and package parasitic impedances, and limited number of I/O pins. In a modern system-on-chip, the power supplies provide the required voltage for the ICs within the overall system (CPUs, GPUs, hard disks, storage, sensors, and others), as well as the analog and digital circuit blocks within the ICs. A regulated 12 V output voltage is often derived off-chip from a 48 V battery [308]. The on-chip DC voltages are significantly lower and range from a fraction of a volt in the low power digital blocks to several volts in the input/output buffers, high precision analog blocks, and storage ICs. Furthermore, to effectively exploit power delay tradeoffs, additional power management techniques such as DVS and DVFS are often employed, further increasing the design complexity of the power delivery system. Thus, to efficiently manage the power delivered to a modern SoC, a methodology to distribute and manage the on-chip power supplies is required.

Traditionally, power is managed off-chip with energy efficient voltage converters (see Fig. 16.1a), delivering high quality DC voltage and current to the electrical grid that reliably distributes the on-chip power. The supply voltage, current density, and parasitic impedances, however, scale aggressively with each technology generation, degrading the quality of the power delivered from the off-chip power supplies to the on-chip load circuitry. The power supply in a package (PSiP) approach with partially off-chip yet in package power supplies is considered an intermediate power supply technology with respect to cost, complexity, and performance [309]. The power is regulated on-chip to lower the parasitic impedance of both the board and package (see Fig. 16.1b). To fully integrate a power converter on-chip, advanced passive components, packaging technologies, and circuit topologies are essential. Several power converters suitable for on-chip integration have recently been fabricated [303, 310–328]. Power supply systems with several on-chip power converters/regulators are commonly encountered to improve the quality of the power delivered within an IC [329–337].

Fig. 16.1

Power delivery system with four voltage domains, (a) off-chip, (b) integrated on-chip, and (c) distributed point-of-load power supplies for voltage conversion and regulation

On-chip power supply integration is an important cornerstone to the power supply design process. A single on-chip power converter is however not capable of supplying sufficient, high quality regulated current to the billions of current loads within the tens of on-chip voltage domains. To maintain a high quality power supply despite increasing on-chip parasitic impedances, hundreds of ultra-small power converters should ultimately be integrated on-chip, close to the loads within the individual multiple voltage domains [310–313]. A distributed point-of-load power supply system is illustrated in Fig. 16.1c.

While the quality of the power supply can be efficiently addressed with a distributed multi-voltage domain system, the limited power efficiency of the on-chip converters is a primary concern for the POL approach . The high power efficiency of the off-chip power converters is traded off for small area and locally regulated currents and voltages.

Three typical topologies, switching mode power supplies (SMPS), switched-capacitors (SC), and linear regulators are depicted in Fig. 16.2. Two switching topologies, SMPS and SC, are discussed, respectively, in Sects. 16.1 and 16.2. A linear topology is reviewed in Sect. 16.3. Some conclusions reviewing the preferable choice of on-chip power supply topology are provided in Sect. 16.4, followed by a brief summary of the chapter in Sect. 16.5.

Fig. 16.2

Typical power conversion topologies (a) switching-mode power supply, (b) switched-capacitor converter, and (c) linear regulator

1 Switching Mode Power Supplies

A typical switching mode power supply (SMPS) converts an input voltage V _IN to an output voltage V _DD , supplying the required current I _DD to the load circuitry. These converters are operated by a switching signal fed into passive energy storage components through a power MOSFET controlled by a pulse width modulator (PWM). A common step down SMPS converter operating as a buck converter is shown in Fig. 16.3. The stored input energy is restored at the output at the required voltage level, maintaining high power efficiency up to a frequency f _s , typically a few megahertz [338]. The operational mode of a buck converter, output voltage, output current, and transient performance are affected by the output LC filter and controller within the feedback loop, as illustrated in Fig. 16.3. The on-chip integration of SMPS converters is greatly complicated due to I/O limitations, and constraints related to the physical size of the passive elements [339]. The area required by the passive components to achieve a specific impedance is inversely proportional to the frequency, and can be reduced in on-chip converters by operating at ultra-high switching frequencies. An SMPS operating at a high frequency is however more affected by the parasitic impedances, degrading the power efficiency of the converter. The area of a buck converter is dominated by the size of the passive elements and is

$$\displaystyle{ A_{Buck} \approx \frac{L} {L_{\square }} + \frac{C} {C_{\square }}, }$$

(16.1)

where L _□ and C _□ are, respectively, the inductance and capacitance per square micrometer of the LC filter.

Fig. 16.3

Buck converter circuit

Voltage regulation is a primary concern for POL power delivery. In discontinuous conduction mode (DCM) [340], the current ripple γ _i I _DD within the inductor L exceeds the output current I _DD , and the voltage V _DD at the output of a converter becomes load dependent, degrading the quality of the delivered power. To support high load regulation, the buck converter is assumed to be loaded with an output current I _DD that exceeds the current ripple ($\gamma _{i}I_{DD} \leq I_{DD}$), yielding expressions for the inductor and capacitor operating in the continuous conduction mode (CCM) [314, 341],

$$\displaystyle{ L = \frac{V _{IN} - V _{DD}} {2f_{s}\gamma _{i}I_{DD}} \cdot \frac{V _{DD}} {V _{IN}}, }$$

(16.2)

$$\displaystyle{ C = \frac{\gamma _{i}I_{DD}} {8f_{s}\gamma _{v}V _{DD}}, }$$

(16.3)

where $\gamma _{v}V _{DD}$ is the voltage ripple at the converter output, and V _DD is the voltage at the load. To satisfy tight load regulation specifications, the output voltage ripple is assumed to range up to 10 % of V _DD (γ _v = 0.1). Substituting (16.2) and (16.3) into (16.4), the area of a buck converter is

$$\displaystyle{ A_{Buck} \approx \left (\frac{(V _{IN} - V _{DD})V _{DD}} {2L_{\square }V _{IN}f_{s}} \right ) \frac{1} {\gamma _{i}I_{DD}} + \left ( \frac{1} {8C_{\square }\gamma _{v}V _{DD}f_{s}}\right )\gamma _{i}I_{DD}. }$$

(16.4)

At low levels of current ripple, the area of a buck converter is dominated by the inductor and increases with smaller $\gamma _{i}I_{DD}$. Alternatively, at larger levels of $\gamma _{i}I_{DD}$, the area of a buck converter is dominated by the size of the capacitor and is proportional to the current ripple. An optimum ripple current $\gamma _{i,OPT}I_{DD}$ therefore exists that minimizes the area of a buck converter for a target output voltage ripple γ _v V _DD , and input and output voltage levels,

where γ _G G is the output conductance ripple and depends upon technology parameters, converted voltages, and the regulation specification. The minimum area of the buck converter is therefore

Thus, in CCM at low current loads ($I_{DD} <\gamma _{G}G \cdot V _{DD}$), the minimum area of a buck converter is dominated by the inductance characteristics and increases with smaller values of I _DD . However, for values of I _DD larger than $\gamma _{G}G \cdot V _{DD}$, the minimum size of a buck converter does not strongly depend on I _DD . Alternatively, both the power MOSFET losses and power dissipated in the LC filter are dominant at different frequencies, conversion voltages, and current levels in CCM. The power dissipated in the power MOSFET comprises the MOSFET switching power ($\propto f_{s}V _{IN}^{2}$) and the resistive power ($\propto R_{ON}I_{DD}^{2}$) dissipated by the effective resistor R _ON of the MOSFET, yielding

$$\displaystyle{ P_{Buck,MOS} = \frac{l_{min}^{2}} {\mu R_{ON}(V _{IN} - V _{T})} \cdot f_{s}V _{IN}^{2} + \frac{4} {3}R_{ON}\frac{V _{DD}} {V _{IN}} I_{DD}^{2}, }$$

(16.9)

where l _min is the minimum channel length, μ is the carrier mobility, and V _T is the threshold voltage [342] of the MOSFET. From (16.9), increasing the effective resistance of the MOSFET reduces the switching power dissipation while increasing the resistive loss. Thus, an optimum resistance R _ON ^OPT exists that minimizes the power dissipated in an MOSFET, yielding

$$\displaystyle{ R_{ON}^{OPT} = \sqrt{\frac{3} {4} \frac{l_{min}^{2}} {\mu (V _{IN} - V _{T})} \cdot f_{s} \frac{V _{IN}} {V _{DD}}} \cdot \frac{V _{IN}} {I_{DD}}, }$$

(16.10)

and

$$\displaystyle{ P_{Buck,MOS}^{MIN} = 2I_{ DD}\sqrt{\frac{4} {3} \frac{l_{min}^{2}} {\mu (V _{IN} - V _{T})} \cdot f_{s}V _{IN}V _{DD}}. }$$

(16.11)

The power dissipated in an LC filter [342] comprises the power losses due to the resistive (ESR _IND ) and capacitive (ESC _IND ) parasitic impedances of the inductor,

$$\displaystyle{ P_{Buck,IND} = \frac{4} {3}ESR_{IND} \cdot I_{DD}^{2} + ESC_{ IND}f_{s} \cdot V _{IN}^{2}, }$$

(16.12)

and the power losses due to the parasitic resistance of the capacitor (ESR _CAP ),

$$\displaystyle{ P_{Buck,CAP} = ESR_{CAP}(\gamma _{i}I_{DD})^{2}. }$$

(16.13)

The total power dissipation and power efficiency $\frac{P_{Load}} {P_{Load}+P_{Buck}}$ of the buck converter are, respectively,

$$\displaystyle\begin{array}{rcl} P_{Buck}& =& \left (\frac{4} {3}ESR_{IND} + ESR_{CAP}\right ) \cdot I_{DD}^{2} + ESC_{ IND} \cdot f_{s} \cdot V _{IN}^{2} \\ & & +2\sqrt{\frac{4} {3} \frac{l_{min}^{2}} {\mu (_{IN} - V _{T})} \cdot f_{s}V _{IN}V _{DD}} \cdot I_{DD}, {}\end{array}$$

(16.14)

$$\displaystyle{ \varphi _{Buck} = \frac{P_{Load}} {P_{Load} + P_{Buck}} = \frac{I_{DD}V _{DD}} {I_{DD}V _{DD} + P_{Buck}}. }$$

(16.15)

Typical passive component parameters, represented by [343–345] and technology parameters [346], are used to demonstrate power and area tradeoffs and trends in buck converters. Current loads from a few milliamperes to several amperes, and input and output voltages of, respectively, 1 and 0.7 V, are considered. The physical area (see (16.7)) and power efficiency (see (16.15)) trends are depicted in Fig. 16.4 for moderate (10 MHz), high (100 MHz), and ultra-high (1 GHz) switching frequencies.

Fig. 16.4

Buck converter (a) physical area, and (b) power efficiency vs. load current for moderate, high, and ultra-high switching frequencies

At low current loads, the power losses of a buck converter in CCM are dominated by the parasitic capacitance of the inductor (ESC _IND ), decreasing the power efficiency at lower I _DD and larger converter size ($A_{Buck} \propto 1/I_{DD}$ for I _DD  < γ _G G ⋅ V _DD ). Alternatively, at high current loads, the power efficiency is dominated by the parasitic resistance of the inductor (ESR _IND ) and capacitor (ESR _CAP ), increasing the power losses of a buck converter at higher I _DD . Thus, a buck converter exhibits a parabolic shaped power efficiency with current in CCM, while the physical size of the converter is reduced at higher currents. Therefore, by targeting high switching frequencies, the preferred current load to convert a voltage with minimum power losses and physical area for a specific switching frequency f _s can be determined. For example, as shown in Fig. 16.4, a preferable current exists for f _s = 100 MHz and f _s = 1 GHz since the maximum power efficiency is achieved at I _DD  > γ _G G ⋅ V _DD but not at f _s = 10 MHz. The minimum power loss in (16.15) is proportional to $\sqrt{ f_{s}}$, significantly degrading the power efficiency at high frequencies. Alternatively, the size of a power converter is proportional to 1∕f _s and decreases at higher frequencies, exhibiting an undesirable tradeoff between the power efficiency and physical size of a buck converter. The high power efficiency of traditional large power converters operating at low frequencies is therefore traded off for smaller physical size at ultra-high switching frequencies.

2 Switched-Capacitor Converters

Another type of switching power supply is a switched-capacitor converter, also referred to as a charge pump (CP) [347]. SC converters utilize capacitors and switches to step up or step down the input voltage based on the principle of charge conservation [289, 308]. The power is typically converted into two non-overlapping time phases, $\varphi _{1}$ and $\varphi _{2}$. During each phase, capacitors are connected in a different configuration, affecting the distribution of charge across the switched capacitors. The operation of a simple one stage CP is illustrated in Fig. 16.5 [347]. During the first phase of the period T _S ($\varphi _{1}: 0 \leq t \leq T_{S}/2$), switches S₁ and S₂ are, respectively, closed and open, and the V_PWM signal is low, charging capacitor C through the input source V _IN  = V _DD , and discharging the output node by the load current I _OUT (see Fig. 16.5a). At the end of $\varphi _{1}$, capacitor C is charged to V _IN , and the output node is discharged by I _OUT ⋅ T _S ∕2. During the second phase ($\varphi _{2}: T_{S}/2 \leq t \leq T_{S}$), switches S₁ and S₂ change state and the signal V_PWM switches from low to high, as shown in Fig. 16.5b). The charge stored on C during $\varphi _{1}$ is redistributed between capacitor C and capacitive load C _L , and supplies the load current I _OUT during phase $\varphi _{2}$. As a result, the voltage at the output increases during each subsequent cycle up to a final asymptotic steady state voltage [347],

$$\displaystyle{ V _{OUT}^{(SS)} = 2V _{ DD} - \Delta V = 2V _{DD} -\frac{I_{OUT}} {f_{s}C}, }$$

(16.16)

where $\Delta V$ is the voltage drop due to charge sharing, and $f_{s} = 1/T_{S}$ is the switching frequency of the converter. The capacitor C behaves as a charge pump in the SC converter and, for sufficiently high switching frequencies, the output voltage in steady state is maintained close to 2V _DD [347]. The voltage drop at the output increases with higher values of I _OUT (see (16.16)), making load regulation difficult in SC converters with high load currents. To limit the voltage drop at the output of an SC converter, a minimum switching frequency f _s, MIN is determined. This voltage drop can also be reduced by increasing the size of the capacitors, trading the larger physical size of the SC converter for improved output voltage regulation. Large power supplies are, however, ineffective for on-chip integration. To enhance the ability of a SC converter to regulate the load, feedback circuitry is added at the expense of lower efficiency of the power conversion process. Alternatively, low current applications that require a low-to-high voltage conversion but not necessarily excellent load regulation (such as wireless monitoring systems, non-volatile memory, and certain mixed-signal systems [348–351]) are natural applications for switched-capacitor converters.

Fig. 16.5

Single stage switched-capacitor converter, (a) phase 1 ($\varphi _{1}: 0 \leq t \leq T_{S}/2$) operation, and (b) phase 2 ($\varphi _{2}: T_{S}/2 \leq t \leq T_{S})$ operation

The power efficiency of a typical switched-capacitor DC-DC converter is primarily limited by heat losses incurred when transferring charge between the switched capacitors P _TRANS , losses in the power switches P _SW , and dynamic power dissipated in the parasitic resistance P _DYN . While the theoretical power efficiency of other switching converters (e.g., SMPS) is 100 %, the power loss due to charge transfer P _TRAN is unavoidable in switched-capacitor converters, degrading the maximum power efficiency of an SC converter by [308]

$$\displaystyle{ P_{TRANS} = \frac{f_{s}} {2} \cdot \frac{CC_{L}} {C + C_{L}} \cdot \left (V _{DD} - \Delta V \right )^{2}. }$$

(16.17)

The switching and dynamic components of the total power loss are strongly dependent upon the design of the SC switches and are comparable with switching and dynamic power losses in other switching converters. Alternatively, power losses due to the parasitic resistance of the wire P _TRANS are specific to the switched-capacitor topology and increase with switching frequency, as described by (16.17). Intuitively, to increase the power efficiency of an SC converter, the capacitors should switch at a lower frequency. This solution is however limited by the minimum frequency constraint f _s  > f _s, MIN determined from (16.16) which is related to the voltage drop and physical size of the converter. To increase the efficiency of an SC converter over a range of frequencies, dynamically reconfigurable topologies should be considered [352]. The physical size, load regulation, and power efficiency characteristics are all important design criteria for integrating on-chip power supplies. Due to the unfavorable tradeoff among these characteristics in an SC converter, switched-capacitor converters are not preferred for distributed on-chip integration in modern heterogeneous systems. An alternative topology that exhibits small physical area and excellent load regulation characteristics is described in the following section.

3 Linear Converters

To provide a specific voltage V _DD and current I _DD to the load circuitry, a linear power supply converts an input DC voltage V _IN using a resistive voltage divider controlled by feedback from the output. The primary drawback of a linear topology is the resistive power losses that increase with a larger V _IN − V _DD voltage drop, which limit the power efficiency to V _DD ∕V _IN . Alternatively, linear converters require a relatively small area, an important characteristic for on-chip integration. Linear regulators can be either analog or, more recently, digital in nature. Analog and digital voltage regulators are described, respectively, in Sects. 16.3.1 and 16.3.2.

3.1 Analog LDO Regulators

A low dropout DC-DC regulator, depicted in Fig. 16.6, is a standard linear converter topology that operates with a low V _IN − V _DD voltage drop. The current that flows through a linear converter is I _IN .

Fig. 16.6

Analog LDO circuit

The current supplied by a linear converter comprises the useful LDO current I _DD that flows to the load, and the short-circuit I _IN − I _DD current dissipated in the bandgap voltage reference and error amplifier. Power and area efficient voltage references have recently been reported [303, 316–318]. The LDO current is, therefore, dominated by the error amplifier and power transistor currents. To mitigate transient voltage peaks while supporting fast changes in the load current, larger currents should be utilized within the error amplifier, increasing the short-circuit current. Alternatively, to satisfy the current load requirements in modern high performance circuits, high currents of up to several amperes are required by the load circuitry. The current flow within an LDO is therefore dominated by the load current I _DD . In this case, both the physical area and power dissipation of a linear converter are primarily dictated by the size and dissipated power of the output power transistor. Thus, the area of an LDO is proportional to the width W of the output transistor, yielding

$$\displaystyle{ A_{Linear} \propto Wl_{min} \propto \frac{I_{DD} \cdot l_{min}^{2}} {\mu C_{OX}(V _{IN} - V _{AMP} - V _{T})^{2}}, }$$

(16.18)

where l _min is the minimum channel length, μ is the carrier mobility, C _OX is the gate oxide capacitance, and V _AMP is the output from the error amplifier. To accommodate the effects of the line and load specifications that may significantly affect the physical size of an LDO, a typical area per 1 mA load [303, 310–318] (see Fig. 16.7) is considered for those LDOs with a high current load. A parabolic relationship is exhibited between the physical area and minimum technology dimensions ($A_{Linear}/I_{DD} \propto l_{min}^{2}$). The ratio $A_{Linear}/I_{DD} = 5 \times 10^{-6}\mathrm{mm}^{2}/\mathrm{mA}$ is based on the 28 nm technology node considered in Fig. 16.8. Typical 28 nm CMOS technology parameters [346], and input and load voltages are assumed in this discussion to demonstrate the need for a large power transistor to supply high current to the load (see Fig. 16.8). The size of the linear converter ranges from $60 \times 60\mbox{ $\upmu $}\mathrm{m}^{2}$ for I _DD = 0.5 A to $150 \times 150\mbox{ $\upmu $}\mathrm{m}^{2}$ for I _DD = 3.5 A (see Fig. 16.8), which can be further reduced with technology scaling ($A_{Linear} \propto l_{min}^{2}$) and advanced design solutions [303, 310–328]. The current can therefore be supplied to the load with an LDO orders of magnitude smaller than a corresponding buck converter.

Fig. 16.7

Physical area of LDO per 1 mA load

Fig. 16.8

Physical area of LDO for typical current loads at 28 nm CMOS technology

The power dissipation of an LDO is

$$\displaystyle{ P_{Linear} \approx \left (V _{IN} - V _{DD}\right )I_{DD}. }$$

(16.19)

Thus, the power loss in a linear converter increases with a higher V _IN − V _DD drop, degrading the power efficiency of the converter. Recent supply voltage trends are illustrated in Fig. 16.9 for the internal core primary voltage V _IN , and typical high and low V _DD levels [346], yielding efficiency bounds within the 70 %–90 % range of the V _DD ∕V _IN ratio shown in Fig. 16.9. Thus, a moderate LDO power efficiency $\varphi _{Linear} = V _{DD}/V _{IN}$ of at least 70 % is typically expected.

Fig. 16.9

Trends in typical (a) high performance (V _HP ), low power (V _LP ), and internal core primary (V _IN ) voltage supplies, and (b) voltage conversion ratios (V _HP ∕V _IN ) and (V _LP ∕V _IN )

3.2 Digital LDO Regulators

Sub/near threshold computing is a promising technique to reduce the power consumed by an IC [353–357]. To provide a stable supply voltage at sub/near threshold levels, tunable low noise voltage regulation below 0.5 V is required. To provide these output voltages with sufficient power efficiency, an analog LDO regulator should operate with low input voltages (e.g., $V _{IN} < 0.7\,\text{V}$ to provide V _DD of 0.5 V with at least 70 % power efficiency). A conventional analog LDO, however, fails to operate at these low input voltages due to the insufficient voltage drop across the individual transistors within the current mirror of the LDO. A digital LDO can however be used to suppress the analog nature of a conventional analog LDO [358, 359].

A digital LDO regulator is typically comprised of a comparator, a digital controller, and an array of MOSFET transistors, as depicted in Fig. 16.10. In this configuration, the output voltage V _DD is continually monitored by the comparator, and the number of simultaneously active MOSFET transistors is dynamically determined by the digital controller based on the comparator output. The power transistor within a conventional analog LDO regulator is replaced in a digital LDO by a digitally controlled array of switches. These digital regulators typically exhibit robust ultra-low voltage regulation and high power efficiency. Alternatively, a slow transient response, large output ripple, and greater physical area are the primary concerns in digital LDO regulators [358, 360, 361].

Fig. 16.10

Digital LDO circuit

4 Comparison of Monolithic Power Supplies

As previously mentioned, the on-chip integration of multiple low voltage power supplies is a primary concern in high performance ICs. An integrated power system should deliver high quality power to multiple loads in an energy efficient manner. The load regulation and power efficiency of individual power supplies within a power delivery system are particularly important and affect the overall performance of the power delivery process. The physical size of a power supply is also critical for integrating multiple on-chip power supplies. The power efficiency, physical size, and load regulation characteristics are compared in this section for the three classical power supply topologies.

The operation of both switching mode power supplies and switched-capacitor converters is based on a two-phase principle. In both topologies, the energy is stored in passive circuit elements during one phase and restored at the output during the other phase. The capacitors and inductors both increase the physical area of the converter, making integration of an on-chip SMPS problematic. Alternatively, SC converters are comprised of only capacitive elements and therefore require less area, making SC converters more suitable for on-chip integration. The high power efficiency and good load regulation characteristics of an SMPS converter are, however, significantly degraded in an SC topology, making switched-capacitor converters inefficient for certain applications.

Linear regulators exhibit small physical size due to the lack of capacitors and inductors, and excellent load regulation characteristics due to the small output impedance. The power efficiency of a linear regulator is limited by the voltage drop across the output power transistor (dropout voltage), making this topology relatively power inefficient when converting large differences between the input and output voltages. Alternatively, the power efficiency of linear regulators increases with lower dropout voltages. To maintain reasonable efficiency, low dropout regulators should be utilized for on-chip integration.

The primary electrical characteristics of SMPS, SC, and low dropout linear topologies are summarized in Table 16.1. Switched-capacitor converters are not preferred for high performance applications due to the limited power efficiency and difficulty in regulating the output voltage under high load variations. The high power efficiency and good load regulation of SMPS converters have made this topology particularly effective for power conversion in high power, high performance applications, such as microprocessors, DSPs, SRAMs, and hard disks [308]. The large physical area and difficulty to integrate on-chip inductive elements degrade the effectiveness of SMPS converters as the need for high quality, distributed on-chip POL power delivery increases. Alternatively, small LDO regulators are a natural choice for on-chip integration. With continuous scaling of the physical feature size and advanced circuit solutions, thousands of ultra-small LDO regulators can potentially be distributed on-chip, close to the loads [191]. Nevertheless, novel design solutions are required to enhance the overall efficiency of LDO based power delivery systems.

Table 16.1 Comparison of SMPS, SC, and LDO topologies for power conversion

The physical area and power efficiency of an LDO and buck converter are shown in Fig. 16.11. Buck converters are more power efficient than alternative LDOs when operating at low switching frequencies. Alternatively, compact buck converters can operate at high switching frequencies. These buck converters, however, exhibit lower power efficiency and are therefore less effective for on-chip integration. Thus, to deliver high quality power to the load circuitry under typical area constraints, on-chip linear regulators should be considered. The moderate power efficiency of an LDO however becomes a significant constraint when the power consumed by the load increases. For example, converting 2 V into 1 V while delivering $\mbox{ $\upmu $}\mathrm{A}$ to the current load results in a 50 % power efficiency and 1V ⋅ 1μA = 1μ W power loss that can possibly be absorbed by the power delivery system. Alternatively, converting 1.25 V into 1 V while delivering 1 mA to the current load results in 80 % power efficiency and a significant 0. 25V ⋅ 1mA = 250μ W power loss that is difficult to tolerate. Thus, for on-chip integration, linear regulators are preferable to switching power supplies, particularly for small input-to-output voltage differences. A heterogeneous power delivery system that efficiently exploits the combined power and area characteristics of linear and switching converters is desirable to enhance the power quality and efficiency of the overall power delivery system while satisfying on-chip area constraints.

Fig. 16.11

LDO and buck converter (a) physical area, and (b) power efficiency for moderate, high, and ultra-high switching frequencies

To better exploit the electrical characteristics of existing power converters, different topologies have recently been combined into hybrid power supplies [187, 313, 362]. For example, linear power supplies can be utilized on-chip for local voltage regulation, whereas off-chip or in-package SMPS can mitigate power losses caused by large voltage drops [187]. In this scheme, the small size and excellent regulation characteristics of an LDO are combined with the high power efficiency of a switching converter, enhancing overall performance and quality. Hybrid topologies exhibit promising qualities for heterogeneous on-chip power delivery, while also posing new research challenges. The co-design of different power converters, overall system-wide power efficiency, dynamic control, and scalability of heterogeneous power delivery systems are topics of growing importance which are discussed throughout this book.

5 Summary

Switching and linear power supply topologies are reviewed in this chapter. The primary conclusions are summarized as follows.

• The physical size of a buck converter is weakly dependent upon the load current and is smaller at higher frequencies

• A buck converter exhibits a parabolic shaped power efficiency with current when operating in the CCM mode

• The preferred current load can be determined to convert a voltage within a buck converter with minimum power losses and physical area for a specific switching frequency f _s

• The minimum power loss of a buck converter is proportional to $\sqrt{f_{s}}$, significantly degrading power efficiency at high frequencies

• The high power efficiency of traditional large switching power converters operating at low frequencies is traded off for smaller physical size at ultra-high switching frequencies

• The switching and dynamic components of the total power loss of SC converters are strongly dependent upon the SC switches and are comparable with switching and dynamic power losses in SMPS converters

• Power losses due to the parasitic resistance of the wire are specific to the switched-capacitor topology and increase with switching frequency, limiting the maximum switching frequency of SC converters

• The minimum switching frequency of an SC converter is constrained by the voltage drop and physical size of the converter

• Switched-capacitor converters are less power efficient than SMPS converters, and are less effective for output regulation than SMPS and LDO converters

• To increase the efficiency of an SC converter over a range of frequencies, dynamically reconfigurable topologies should be considered

• The power loss in a linear converter increases with a higher V _IN − V _DD drop, degrading the power efficiency of the converter

• The efficiency of a linear converter for typical supply voltages is typically within the 70 %–90 % range of the V _DD ∕V _IN ratio

• Linear regulators are preferable to switching power supplies for small input-output voltage differences

• Existing power converter topologies exhibit an undesirable tradeoff among power efficiency, load regulation, and physical size

• A heterogeneous power delivery system that efficiently exploits the power and area characteristics of linear and switching converters is desirable to enhance the power quality and efficiency of the entire power delivery system while satisfying on-chip area constraints