Abstract
From raw silicon to a finished integrated circuit (IC), a typical semiconductor manufacturing process involves wafer fabrication, wafer probe, assembly, and final test. Before an IC is delivered to customers, it undergoes final test where its overall functionality is verified. This stage is where low yield issue is often encountered and with yield having a direct impact on a company’s revenue, it is considered a critical key process indicator. To the best of the author’s research, this is the first study to use both continuous and categorical front-end (excluding WAT parameters) and back-end variables to predict final test yield through regression analysis. A three-year amount of real production data was used to train, validate, and evaluate 11 different regressors. A genetic algorithm is also implemented for feature reduction. Results show that the optimized Bagging Regression model has a R2 score of 0.6813 with an average mean absolute error of 0.3902%.
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Dimaculangan, R.V., de Luna, R.G., Rosales, M.A., Magsumbol, JA.V., Tubola, O.D. (2023). Semiconductor Manufacturing Final Test Yield Prediction Using Regression with Genetic Algorithm-Based Feature Selection. In: Vasant, P., et al. Intelligent Computing and Optimization. ICO 2023. Lecture Notes in Networks and Systems, vol 854. Springer, Cham. https://doi.org/10.1007/978-3-031-50151-7_11
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DOI: https://doi.org/10.1007/978-3-031-50151-7_11
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