Keywords

1 Introduction

TR Limiters are usually employed in radar systems to protect the high sensitive receiver from undesired large input signal, thus relaxing the linearity specifications of radar receivers, [1, 2]. Typical Transmitter-Receiver (TR) limiters make use of PIN diodes in order to implement a voltage-controlled resistors. The ability showed by such devices to manipulates large amounts of RF power, making use of low DC excitation is fundamental in TR limiters [3]. PIN diodes based TR limiter configurations are well known and the principle of operation is largely discussed in literature [4, 5]. The accurate characterization of PIN across the operative bandwidth is crucial for accurate TR limiter design.

Basically a TR limiter consists in a waveguide with one or more resonant cavities. Each of them incorporate a PIN diode mounted on a structure, the post, that allows to change the position of the diode inside the corresponding cavity [6]. Each of the series of posts and diodes became a RF short circuit when the diode enter in ON state, at a frequency which depends upon the post length, thus the diode position within the cavities; conversely, in the OFF state the diodes shouldn’t affect the signal propagation across the waveguide. In this paper we present a method to characterize the intrinsic portion of a PIN diode, for its use in predicting the operative frequency of the limiter on the basis of the post length. The PIN diode is considered embedded in a WR90 waveguide, with the contribution of the waveguide de-embedded by means of electromagnetic simulations. The method is suitable for estimation of the TR limiter operation across the X-band in both the OFF and ON steady states.

The anlystical treatment for the diode extraction, the electromagnetic simulations and the experimental results are presented in the paper.

2 Intrinsic PIN Diode Characterization

One of the main issue in limiter design consist in the availability of an accurate model of the PIN diode. In the past year many linear and non linear model were proposed. Some of them were physically based, while other were fully behavioral. Among the others, some interesting approaches were illustrated in [7,8,9]. All these methods are aimed to describe the whole discrete PIN diode, included in its package. On the contrary the method proposed in the present paper is oriented to the identification of the intrinsic portion of a discrete PIN diode, for a better prediction of the limiter operating frequency as function of the diode in the waveguide cavity. The accurate geometrical description of the diode is obtained by means of a series of microscopic measurements. The mechanical characterization of the intrinsic part of the diode is necessary for the correct identification of the intrinsic diode model. The intrinsic part of the PIN diode corresponds to the Silicon die as illustrated in Fig. 1, which describes the internal structure of the diode adopted in this work. The Silicon die is bonded to the cathode through a couple wire. This approach enables to include all package parasites within the EM simulation as well as the effect of the interaction of the package with the JIG structure.

Fig. 1.
figure 1

Accurate interior mechanical description of the discrete PIN diode under test (from CST EM simulator)

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The intrinsic portion of the diode is described by means its S- Parameter Matrix \(S_{diode}\left( V_{bias},\omega \right) \) where \(\omega \) and \(V_{bias}\) correspond, respectively, to the whole X-band radial frequency and to the ON and OFF state bias. For the \(S_{diode}\) identification we follows the de-embedding approach introduced in [10]. The procedure is schematically described in Fig. 2. The latter enables the identification of the \(S\left( 1\times 1\right) \) matrix describing the intrinsic portion of the diode. The procedure make use of the \(S\left( 2\times 2\right) \) matrix obtained by VNA measurements while the effect of both the JIG and the diode package are described by an \(S\left( 3\times 3\right) \) matrix obtained by a accurate EM simulations as described in Fig. 3.

Fig. 2.
figure 2

Schematic description of the de-embedding method implemented for the extraction of \(Y_{diode}\left( V_{bias},\omega \right) \).

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Fig. 3.
figure 3

Schematic of the EM simulated Test JIG used to extract the intrinsic PIN diode S parameter description.

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The de-embedding method implemented in the present work is described by the (1) and the (2).

$$\begin{aligned} S_{(1\times 1)} = M^{-1}, \end{aligned}$$
(1)

where M is a (\(1\times 1\)) matrix obtained starting from the (\(2\times 2\)) measured S matrix and the and the (\(3\times 3\)) simulated S matrix.

$$\begin{aligned} {\textbf {M}} = \left[ S_{31}~S_{32}~S_{33}\right] \cdot \left[ \begin{array}{c} {\left[ {\textbf {A}}-{\textbf {G}}\right] }^{-1}\cdot {\textbf {D}}\\ 1\\ \end{array} \right] , \end{aligned}$$
(2)

where:

\({\textbf {A}}\) = Measured S-paramenter matrix

\({\textbf {G}}\) = (\(2\times 2\)) minor of the simulated (\(3\times 3\)) S matrix.

\({\textbf {D}}\) = (\(2\times 1\)) column vector of the 3rd column of the (\(3\times 3\)) S matrix.

\(\left[ S_{31}~S_{32}~S_{33}\right] \)= 3rd row of the simulated (\(3\times 3\)) S matrix.

3 Test JIG and Measurements

A test JIG was designed to both enable the measurements for the de-embedding procedure and to verify the predictive performance of the model, it is based on a WR90 waveguide and emulates the limiter operation across the X-band. The JIG was developed using the full-3D EM simulator CST as illustrated in Fig. 3. The prototype of the designed JIG is illustrated in Fig. 4.

Fig. 4.
figure 4

Experimental test JIG for the PIN diode extraction and model validation; this part emulates the limiter operation across X-band.

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A measurement set-was implemented as illustrate in Fig. 5, by means of a VNA calibrated on WR90 waveguide standards. By the test JIG, the PIN diode was polarized in both ON and OFF condition (Vd = 10 V and Vd = 0 V) using an external power supply. A set of S-parameter broadband measurements were carried out, considering 9 different diode positions within the JIG, for both the ON and OFF diode state.

Fig. 5.
figure 5

Experimental measurement set-up for PIN diode extraction and model validation across X-band.

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Six out of the nine double set of measured data were used in the de-embedding procedure to extract the corresponding \(S\left( 1\times 1\right) \) matrix, describing the intrinsic portion of the diode while the remaining three sets of measures were used to validate the model.

4 Intrinsic PIN Diode Modeling

The procedure to extract the intrinsic PIN diode circuital model in the ON and OFF condition makes use of the corresponding six \(S\left( 1\times 1\right) \) matrix, extracted from the measures obtained varying the position of the diode inside the JIG. As the diode is polarized in the same state (same Vd) in the all the six ON and six OFF position, it seems reasonable to expect the extracted matrices to be equal. On the contrary these S matrix slightly differ one each other due to numerical noise and higher order effect not taken into account by the model description of Sect. 2. As a consequence the \(S\left( 1\times 1\right) \) representative of the ON and OFF states were calculated as average value of the six extracted one.

The extraction of the components included in the circuital model was based on the averaged intrinsic matrix, extracted for the six screw positions, which are depicted in Fig. 7 for both the ON and OFF state. The implemented circuital model was based on a very simple topology, which is the same for both the two states. The latter is based on a series inductance, L, followed by a parallel R, C circuit. The proposed topology is illustrated in Fig. 6. The components value were calculated by means of a best fitting procedure and lead to the values illustrated in Table 1. Comparison between the ON and OFF model and the averaged ON and OFF \(S\left( 1\times 1\right) \) matrices are shown in Fig. 7. The latter highlight a good agreement between the extracted intrinsic average S parameter and the one obtained with the intrinsic model.

Results illustrated in Table 1, show that the inductance is almost constant in both the states, while the capacitance and resistance undergo a significant change from ON to OFF (from 3.8 to 0.17 pF and from 8 to 1100 \(\Omega \) respectively).

Fig. 6.
figure 6

Circuit model topology of the intrinsic PIN diode, the catode is considered connected to ground.

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Fig. 7.
figure 7

Comparison between averaged extracted intrinsic diode data and simulated one by circuit of Fig. 6.

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Table 1. ON and OFF model value.
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5 Experimental Results

The three sets of measures, which correspond to different diode depths into the waveguide, in both the ON and OFF condition, not included in the diode characterization phase, were used to validate the model. To this aim three corresponding EM simulations of the JIG considering the different position of the screw in the post within the WR90 guide were carried out and used in conjunction with the extracted circuital model for the ON and OFF described in the previous section. The aims were to predict the behavior of the limiter in these specific screw positions. Results of this simulations are illustrated in Fig. 8 in comparison with measured data at the corresponding screw position within the limiter. Figure shows on the left the OFF state while on the right the ON state.

Fig. 8.
figure 8

Comparison between measurement and simulated data, in terms of S11 (continuos) and S21 (dashed) for different diode positions and for both OFF state: left column, ON state: right column.

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6 Conclusion

In the present paper a procedure to extract the intrinsic PIN diode lumped element model was presented. The method is based on the optimization of a mathematical technique aimed at the identification of the intrinsic portion packaged diode. The approach enable a simple and fast modeling of the PIN Diode die as shown by the corresponding model which uses only three lumped elements for both ON and OFF state. The effects of parasites due to the package are absorbed by the EM simulation of the JIG which includes an accurate description of the diode mechanics. This approach shows advantage both in the intrinsic extrapolation procedure as well as in the prediction of the structure behavior across the whole X-band. The illustrated results highlight an optimum matching between measurements and simulation.