Process Variability-Aware Analytical Modeling of Delay in Subthreshold Regime with Device Stacking Effects

Abstract

In advanced process nodes, circuit design is sensitive to increasing process variability, thereby limiting performance enhancements. As the subthreshold operation is suitable for ultra low power applications, designing process variability-aware circuits is challenging. Accurate, reliable, and fast analytical models to estimate process variability impact on performance are critical in bridging the gap between circuit design and manufacturing. Hence, analytical models are proposed to model delay variability due to variations in device geometry and electrical parameters. The subthreshold current variation at the device level and delay at circuit level are explored due to simultaneous variations in gate length, width, and threshold voltage. The characterization of rising and falling edge delay variability of NAND/NOR structures in 32 nm PTM technology is based on distributions generated using Monte Carlo analysis and validated against SPICE. The model-based mean prediction error is below 0.12%, and the computational burden is reduced by 70X–500X compared to SPICE simulations. Further, it is demonstrated that the models hold good for a wide range of subthreshold operation, with supply voltage ranging from 0.18 V–0.23 V, with 0.2 V being the nominal supply voltage for subthreshold circuit operation.

B. P. Harish—Senior Member, IEEE.

1 Introduction

Despite the design maturity of the super-threshold regime, the subthreshold design has gained significant traction due to the rapid growth of battery-powered portable systems. Subthreshold circuits have achieved power reduction of several orders of magnitude in contrast to their super-threshold counterparts. Subthreshold circuits are the technology choice for ultra low power VLSI applications with stringent energy constraints since such circuits offer low-energy solutions with low to moderate performance. Though low supply voltage and low operating current results in significant power savings, the subthreshold circuit design still poses multiple challenges. This can be attributed to its high susceptibility to Process (P), Voltage (V), and Temperature (T) variations that threaten to impact the performance metrics, and in turn, their predictability.

The Maximum Clock Frequency (FMAX) distribution model statistics reveal that significant performance degradation results from systematic within-die parameter fluctuations [1], thereby elucidating device architecture designs and new circuit design methodologies for improving the circuit performance of future Gigascale Integration (GSI). The circuit design is still not very promising in the subthreshold regime, mainly when sub-90 nm nodes are considered since process tolerances during the VLSI fabrication process are not tight enough and can result in significant gate delay variations of up to 300% [2]. The evaluation of process variation impact on propagation delay is modeled analytically and validated against the mixed-mode simulations. Simulation studies have revealed that gate length (${L_{g}}$), halo dose, and oxide thickness (${T_{ox}}$) are the dominant set of process parameters affecting both device as well as circuit variability [3]. Studies reveal that threshold voltage (${V_{th}}$) and ${L_{g}}$ are the significant sources of die-to-die variations and within-die variations, with the variance in ${L_{g}}$ and ${V_{th}}$ being more than 30% and 10%, respectively [4]. Although the corner models have been the mainstay of the IC industry for many years, they assumed a “one-size-fits-all” solution, i.e., within a die, all the devices would exhibit either the worst-case or best-case feature at the same time. While the “safe” method offers guard-bands for process parameter variations, it introduces pessimism in the design, resulting in significant circuit performance loss. Consequently, process parameter variation on delay modeling opens up new design challenges for timing sign-off.

From a design perspective, researchers have attempted to address the variability challenges by analysing the impact of single parameter variations on delay. The subthreshold delay variability due to PVT variations is characterized by first-order analytical models whose model accuracy has been validated through SPICE simulations on a 130 nm CMOS process. The modeling error is within 10%, 12%, and 0.9% for ${V_{th}}$, supply voltage (${V_{DD}}$), and temperature variations, respectively [5]. To characterise PVT variations that occur in the subthreshold operation, an analytical model to estimate delay variability is presented with an error of 1% for process, 14.6% for supply voltage, and 6.8% for temperature variations, respectively, with the accuracy improvement achieved through a compensation factor [6]. The absence of modeling both the rising edge and the falling edge delay impacts the completeness of the model. Based on the subthreshold transient current model, output waveform and coupling capacitance equivalence, an analytical delay variability model is derived for the inverter chain under SMIC 40 nm technology node [7]. An analytical model for gate delay variability is proposed, taking into account variations in ${V_{th}}$ alone and transient variation of device on-current during switching with DIBL effects [8]. A linear compositional model for delay prediction is proposed, i.e., the significant model parameters are first gathered through Monte Carlo simulations, which are then linearly propagated from device to circuit. It is assumed that ${V_{th}}$ variations follow an Inverse Gaussian Distribution (IGD) [9]. Assuming a log skew-normal distribution for ${V_{th}}$ variation, delay variability of the stacked gates is evaluated using the bivariate linear model [10]. In [11], the delay variability of a generic logic gate is computed by assuming the correlation between the stacked transistors. Furthermore, the variational model is validated only under specific process corners of ${V_{th}}$ variation.

The existing models suffer from the following limitations: Though accurate models for subthreshold delay variability have been proposed for static CMOS inverters with ${V_{th}}$ variations alone in [5,6,7], the models do not account for the effects introduced by the transistor stack. In [8,9,10,11], the stacking effect has been considered, but the delay variability models incorporate ${V_{th}}$ variations alone. The modeling methodology of [5,6,7,8,9,10,11] accounts for the exponential dependence of delay on a single parameter, i.e., ${V_{th}}$ and hence fail to model concurrent variations in device geometry parameters to depict the linear dependence on delay. The existing works fail to account for concurrent variations in device electrical (${V_{th}}$) and geometry parameters ($L_{g}$ and W). Though the existing models have effectively considered the single parameter (${V_{th}}$) variation impact on subthreshold delay, they cannot be further extended to model simultaneous variations since the existing models focus only on the exponential relationship of ${V_{th}}$ with drain current and not linear relationship of geometry parameters.

Process variations significantly impact all the aspects of circuit performance and pose a major challenge to robust IC design in subthreshold regime. Consequently, improving robustness and resolving the performance variability concerns during the early design phase is crucial. This requires accurate and reliable subthreshold analytical models for process variability characterization in modern processes.

To address these shortcomings, the contributions of the proposed work are as follows: The threshold voltage (${V_{th}}$) being a significant parameter contributing to delay variability in the subthreshold regime, a simple and accurate variation-aware delay model is proposed, ensuring a realistic estimation of delay in the presence of its variation. The proposed delay variability model accounts for simultaneous variations in multiple process parameters, namely, ${V_{th}}$, ${L_{g}}$, and W ensuring a bridge between design CAD and technology CAD. To the best of the author’s knowledge, there have been no variability models to account for the delay dependency on simultaneous variations in ${V_{th}}$, ${L_{g}}$, and W. To verify the model scalability with respect to circuit size, the efficacy and adequacy of the models are validated, over a wide range of subthreshold operation, using NMOS and PMOS stacks as in NAND and NOR gate, respectively. This demonstrates that the proposed models are efficacious in estimating the circuit delay variability of any size, complexity, and topology. The results demonstrate that the proposed delay variability models are about 70X–500X computationally more efficient than SPICE simulations in generating the delay distributions, with the mean error being less than 0.12%.

The rest of the paper is structured as follows: Sect. 2 outlines the motivation for the proposed work, principles of modeling methodology, and the subthreshold analytical delay variability models of NMOS stack and PMOS stack in terms of ${V_{th}}$, ${L_{g}}$, and W. Section 3 presents the characterization of delay distributions of NMOS stack (NAND gate) and PMOS stack (NOR gate) with SPICE simulation-based validation. Section 4 summarizes the results.

2 Motivation and Principles of Modeling Methodology

The process flow of chip fabrication involves variability issues at every process step. Process variability has a profound impact on delay in the nanometer regime, translating into either parametric or catastrophic chip failure. Hence, there is a need to capture the impact of variability during the early phase of design flow to minimize the “almost-working” chips from being discarded, thereby increasing the chip yield. Further, the need for robust design has led to the development of analytical delay variability models, accounting for process variability. In the subthreshold regime, the propagation delay is ruled by an exponential (${V_{th}}$) and linear dependence on parameters (${L_{g}}$ and W). Thus, the shift in their magnitudes can be very critical, impacting the delay predictability.

In this direction, first an analytical model for delay variability is derived accounting for variations in the dominant factor, ${V_{th}}$, in the subthreshold region. Further, the circuit-delay variability is evaluated in the presence of concurrent fluctuations in the electrical and geometry parameters of the transistor.

Fig. 1.

Block diagram of subthreshold delay modeling in the presence of process variations.

Figure 1 illustrates the underlying relationship between the device/circuit parameters and process parameters. The device geometry variations and fluctuations in the doping levels incurred by process variations impact the electrical characteristics of the device in unique and often subtle ways, which in turn varies the circuit performance parameters. Thus, it is desirable to map the variations in underlying process parameters such as ${V_{th}}$, ${L_{g}}$, and W to the delay variations at the circuit level. To model the statistical variations of gate delay, the variations in electrical and geometry parameters of the transistor are assumed to follow a Gaussian (normal) distribution. According to the experimental results [12], the spread in the parameters are projected to remain at ±3$\sigma$ = ±10%, with ±3$\sigma$ corresponding to variations around the nominal value. The delay variability analysis is executed in three phases:

• 1. variations in ${V_{th}}$: $\varDelta {V_{th}}$

• 2. variations in ${V_{th}}$ and ${L_{g}}$: $\varDelta {V_{th}}$ and $\varDelta {L_{g}}$

• 3. variations in ${V_{th}}$, ${L_{g}}$, and W: $\varDelta {V_{th}}$, $\varDelta {L_{g}}$, and $\varDelta {W}$

The execution of the primary phase involves $\varDelta {V_{th}}$ alone while maintaining other parameters constant. The secondary phase entails simultaneous variations in ${V_{th}}$ and ${L_{g}}$, with width, W, as a constant parameter. The last phase involves simultaneous variations of all the parameters. While the variability analysis in the first phase represents delay fluctuations with respect to a single parameter, the second and last phase characterizes delay variations under multiple parameters. To characterize the variations in rising edge and falling edge gate delay distributions, the proposed model-driven rigorous Monte Carlo analysis is performed. The delay distributions obtained by model calculations are validated against SPICE Monte Carlo simulations.

The proposed analytical framework emphasizes on the absolute amount of variability regardless of the taxonomy of process variability. In prior work [13], a static CMOS inverter was used as a reference circuit to validate the delay variability model. However, the adequacy and efficacy of the models were not evaluated in the case of simultaneous variations in device width and the transistor stacking effect with multiple inputs. To verify the adequacy and scalability of the models with respect to circuit size, there is a need to address the scalability requirements.

2.1 Analytical Delay Distribution Model for NMOS Stack

${V_{th}}$ is the most dominant device electrical parameter in the subthreshold region due to the inverse exponential dependence of drive current on ${V_{th}}$. A simple and accurate analytical model for computing the delay variability is presented in terms of three dominant parameter variations, ${V_{th}}$, ${L_{g}}$, and W. The gate delay model is derived based on the CV/I metric.

To elucidate the DIBL effect, being prominent in short-channel MOSFETs, ${V_{th}}$ can be modeled as [14]:

$$\begin{aligned} V_{th} = V_{th0} - \eta V_{ds} \end{aligned}$$

(1)

where ${V_{th0}}$ is the zero-bias threshold voltage and $\eta$ represents the DIBL coefficient.

According to the BSIM4 MOS model, the drain-source current of NMOS in the subthreshold regime is given by [15]:

$$\begin{aligned} I_{sub} =I_{0} e^{\frac{(V_{gs}-V_{th0})}{m V_{t}}} e^{\frac{\eta V_{ds}}{m V_{t}}}(1-e^{\frac{-V_{ds}}{V_{t} }}) \end{aligned}$$

(2)

$$\begin{aligned} \text {As,}\ e^{\frac{-V_{ds}}{V_{t} }} \cong 0 \end{aligned}$$

$$\begin{aligned} I_{sub} =I_{0} e^{\frac{(V_{gs}-V_{th0})}{m V_{t}}} e^{\frac{\eta V_{ds}}{m V_{t}}} \end{aligned}$$

(3)

$$\begin{aligned} \text {where } I_0= \mu _n C_{ox} \frac{W}{L_g}(m-1)V_t^2 \end{aligned}$$

(4)

${V_{t}}({=\frac{kT}{q}})$ is the thermal voltage, m is subthreshold slope coefficient, $\mu _{n}$ is the electron mobility, $\frac{W}{_{g}}$ is the transistor aspect ratio, and ${C_{ox}}$ is the oxide capacitance per unit area. The existing equation from BSIM4 model is considered as the starting point for delay variability modeling.

The propagation delay ($\tau _d$) is given by:

$$\begin{aligned} \tau _{d}=\frac{C_{L} V_{DD}}{I_{sub}} \end{aligned}$$

(5)

where ${V_{DD}}$ is the supply voltage and ${C_{L}}$ is the load capacitance.

From Eqs. (3)–(5), it follows that ${I_{sub}}$ has an inverse exponential relationship with ${V_{th}}$ and linear dependence on ${L_{g}}$ and W. This dependence makes it necessary to consider these three parameter variations in order to account for delay variability.

To demonstrate the model scalability with respect to circuit size, the efficacy and adequacy of the models have to be validated using NMOS and PMOS stacks as in NAND and NOR gate, respectively. In [16], the NAND gate delay is computed by replacing the gate with an equivalent inverter. In the subthreshold regime, this method of merging the stacked transistors into a single equivalent transistor is no longer a suitable choice since the intermediate node voltage is non-negligible [8].

Fig. 2.

Stacked NMOS transistors in the NAND gate.

The stacking of NMOS transistors in a NAND gate is as shown in Fig. 2. The subthreshold current through the NMOS devices (M1 and M2) in the pull-down network of the NAND gate is expressed as [17]:

$$\begin{aligned} I_{sub,M1} =I_{01} e^{\frac{(V_{gs,M1}-V_{th0,M1}+ \eta V_{ds,M1} )}{m V_{t}}}(1-e^{\frac{-V_{ds,M1}}{V_{t} }}) \end{aligned}$$

(6)

$$\begin{aligned} I_{sub,M2} = I_{02} e^{\frac{(V_{gs,M2}-V_{th0,M2}- \gamma V_{sb,M2}+\eta V_{ds,M2} )}{m V_{t}}} (1-e^{\frac{-V_{ds,M2}}{V_{t} }}) \end{aligned}$$

(7)

where $\gamma$ = body bias coefficient, ${V_{gs,M1}} = {V_{DD}}, {V_{ds,M1}} = {V_{X}}, {V_{gs,M2}} = {V_{DD}} - {V_{X}}, {V_{sb,M2}} = {V_{X}}, {V_{ds,M2}} = {V_{DD}} - {V_{X}}$ and ${V_{X}}$ is the intermediate node voltage in the stack.

Equations (6) and (7) can be rewritten as:

$$\begin{aligned} I_{sub,M1} =I_{01} e^{\frac{(V_{DD}-V_{th0,M1}+ \eta V_{X} )}{m V_{t}}} (1-e^{\frac{-V_{X}}{V_{t} }}) \end{aligned}$$

(8)

$$\begin{aligned} I_{sub,M2} = I_{02} e^{\frac{(V_{DD}-V_{X}-V_{th0,M2}- \gamma V_{X}+\eta (V_{DD}-V_{X}))}{m V_{t}}} (1-e^{\frac{-(V_{DD}-V_{X})}{V_{t} }}) \end{aligned}$$

(9)

The following model assumptions are reasonably valid with acceptable accuracy:

• 1. Variations in geometrical parameters of M1 and M2 are negligible, i.e., ${I_{01}} = {I_{02}} = {I_{0}} = \mu _n C_{ox} \frac{W}{L_g} (m-1)V_t^2$

• 2. ${V_{th0,M1}} = {V_{th0,M2}}$ [8]

• 3. $e^{\frac{-(V_{DD}-V_{X})}{V_{t} }} \approx 0$ [15]

• 4. Since ${V_{X}} \approx 0.1 {V_{DD}}$, $\eta {V_{X}} \approx 0$ [17]

The resulting expression for ${V_{X}}$ is obtained by equating Eqs. (8) and (9) as follows:

$$\begin{aligned} I_{sub,M1} = I_{sub,M2} \end{aligned}$$

(10)

$$\begin{aligned} V_{X} = V_{t} ln(e^{\frac{\eta V_{DD}}{m V_{t}}} + 1) = \frac{kT}{q} ln(e^{\frac{\eta V_{DD}}{m V_{t}}} + 1) \end{aligned}$$

(11)

Substituting for ${V_{X}}$ in Eq. (8) results in:

$$\begin{aligned} I_{sub} = I_{sub,M1} = I_{0} e^{\frac{(V_{DD}-V_{th0}+ \eta V_{t} (ln(e^{\frac{\eta V_{DD}}{m V_{t}}} + 1)))}{m V_{t}}}(1-e^{\frac{-V_{t}(ln (e^{\frac{\eta V_{DD}}{m V_{t}}} + 1))}{V_{t} }}) \end{aligned}$$

(12)

where ${I_{sub,M1}}$ denotes the worst-case subthreshold current.

Subthreshold Analytical Delay Modeling Under $\boldsymbol{\varDelta {V_{th}}}$

The delay model of $\tau _d$ is dependent on $\varDelta {V_{th}}$ as depicted by the analytical model of Eq. (5).

Substituting for ${I_{sub}}$ in Eq. (5) from Eqs. (4) and (12), and by differentiating the equation for $\tau _d$ with respect to $\varDelta {V_{th}}$ results in:

$$\begin{aligned} \varDelta \tau _{d\varDelta V_{th,NAND}} \equiv \frac{\delta \tau _{d}}{\delta V_{th}}= \frac{K_{1}C_{L} V_{DD}}{I_{0} {m V_{t}} e^{\frac{(V_{DD}-\varDelta V_{th}+ \eta V_{t} (ln (e^{\frac{\eta V_{DD}}{m V_{t}}} + 1)))}{m V_{t}}} (1-e^{\frac{-V_{t} (ln(e^{\frac{\eta V_{DD}}{m V_{t}}} + 1))}{V_{t} }})} \end{aligned}$$

(13)

where $\varDelta \tau _{d}\varDelta V_{th,NAND}$ is the NMOS stack delay variability under ${V_{th}}$ variations alone and ${K_{1}}$ represents the model fitting parameter. Further, ${V_{th}}$ also depends on ${T_{ox}}$, doping concentration, Random Dopant Fluctuation (RDF), and line edge roughness. The analytical model is derived by considering that ${V_{th}}$ is a composite function of all these parameters.

Subthreshold Analytical Delay Modeling Under $\boldsymbol{\varDelta {V_{th}}}$ and $\boldsymbol{\varDelta {L_{g}}}$

Due to the inverse proportional dependence of ${I_{0}}$ on ${L_{g}}$, gate length variation impacts the delay variation proportionally. Considering simultaneous variations in ${V_{th}}$ and ${L_{g}}$, the gate delay variability model is expressed as:

$$\begin{aligned}&\varDelta \tau _{d\varDelta V_{th},\varDelta L_{g,NAND}} = \nonumber \\&\frac{K_{2}C_{L}V_{DD}}{\mu _n C_{ox}(m-1)V_t^2{m V_{t}}\frac{W}{\varDelta L_{g}}e^{\frac{(V_{DD}-\varDelta V_{th}+ \eta V_{t} (ln (e^{\frac{\eta V_{DD}}{m V_{t}}} + 1)))}{m V_{t}}} (1-e^{\frac{-V_{t} (ln (e^{\frac{\eta V_{DD}}{m V_{t}}} + 1))}{V_{t} }})}\nonumber \\ \end{aligned}$$

(14)

where $\varDelta \tau _{d} \varDelta {V_{th}}$, $\varDelta {L_{g,NAND}}$ is the NMOS stack delay variability under ${V_{th}}$ and ${L_{g}}$ variations, and ${K_{2}}$ represents the model fitting parameter. Continuing to use Eq. 13, $\varDelta {L_{g}}$ is passed to evaluate the impact of gate length variation on delay variability.

This analytical approach of estimating delay variability with concurrent process parameter variations is rigorous compared to the mathematical techniques of linear interpolation and linear superposition as reported in [3].

Subthreshold Analytical Delay Modeling Under $\boldsymbol{\varDelta {V_{th}}}$, $\boldsymbol{\varDelta {L_{g}}}$, and $\boldsymbol{\varDelta {W}}$

Applying the same above methodology, modeling of gate delay variation under simultaneous fluctuations in ${V_{th}}$, ${L_{g}}$, and W takes the form:

$$\begin{aligned}&\varDelta \tau _{d\varDelta V_{th},\varDelta L_{g},\varDelta {W,_{NAND}}} =\nonumber \\&\frac{K_{3}C_{L}V_{DD}}{\mu _n C_{ox}(m-1)V_t^2{m V_{t}}\frac{\varDelta W}{\varDelta L_{g}}e^{\frac{(V_{DD}-\varDelta V_{th}+ \eta V_{t} (ln (e^{\frac{\eta V_{DD}}{m V_{t}}} + 1)))}{m V_{t}}} (1-e^{\frac{-V_{t} (ln (e^{\frac{\eta V_{DD}}{m V_{t}}} + 1))}{V_{t} }})}\nonumber \\ \end{aligned}$$

(15)

where $\varDelta \tau _{d\varDelta V_{th},\varDelta L_{g}, \varDelta W,_{NAND}}$ is the NMOS stack delay variability under ${V_{th}}$, ${L_{g}}$, and W variations and ${K_{3}}$ represents the model fitting parameter. Continuing to use Eq. (14), $\varDelta$W is passed to evaluate the impact of gate width variation on delay variability.

For simultaneous variations in multiple parameters, partial differentiation is not considered for the lack of resulting model accuracy due to complex relationships. Owing to the absence of similar delay variability models in the current literature, the proposed analytical models have not been compared against other works.

2.2 Subthreshold Delay Variability Model for PMOS Stack

Fig. 3.

Stacked PMOS transistors in the NOR gate.

The stacking of PMOS devices in a 2-input NOR gate is depicted in Fig. 3. The intermediate node between M1 and M2, annotated using the voltage ${V_{X1}}$ is obtained by solving ${I_{sub,M1}} = {I_{sub,M2}}$. Thus, the expression for ${V_{X1}}$ is expressed as:

$$\begin{aligned} V_{X1} = {\frac{(1+ \eta + \gamma )V_{DD}}{ (1 + \gamma + 2\eta ) } } \end{aligned}$$

(16)

Applying the same methodology as in NMOS stack (NAND gate), the subthreshold delay variability of a NOR gate with respect to variations in ${V_{th}}$ alone, ${V_{th}}$ and ${L_{g}}$, and ${V_{th}}$, ${L_{g}}$, and W are derived.

The ability to compute the delay variability of subthreshold digital circuits of any complexity, size, and topology demonstrates the versatility of the proposed analytical models. The model fitting parameters can be easily computed for different NMOS/PMOS stack depths using a curve-fitting tool.

3 Results and Discussion

3.1 NMOS Stack Delay Distributions for Subthreshold Operation

Predictive Technology Model (PTM) [18] file of a 32 nm process node is used to design a two-input NAND gate with ${V_{th0}}$ (NMOS) = 0.3558 V and ${V_{th0}}$ (PMOS) = -0.24123 V, and an optimal supply voltage of ${V_{DD}}$ = 0.2 V for subthreshold circuit operation. The NAND gate is simulated by setting the pulse inputs with rise and fall times of 50 ps, and ${C_{L}}$ = 1 aF [6], accounting for the area and side-wall capacitances of NMOS and PMOS devices. The falling edge gate delay, due to A input, is denoted as $\tau {_{pHLA}}$. Similarly, $\tau {_{pHLB}}$ and $\tau {_{pHLAB}}$ denote falling edge delay due to B input and when both A and B inputs are tied together, respectively. The nominal delay values of $\tau {_{pHLA}}$, $\tau {_{pHLB}}$, and $\tau {_{pHLAB}}$ obtained by SPICE simulations are 314.33 ps, 246.71 ps, and 277.95 ps, respectively.

Table 1. Statistics of $\tau {_{pHL}}$ for ±10% variations in ${V_{th}}, {L_{g}}$, and W for NMOS stack with ${V_{DD} = 0.2 V}$

Assuming that the parameters ${V_{th}}$, ${L_{g}}$, and W follow Gaussian (normal) distribution with ±3$\sigma$ corresponding to ±10% of their nominal, the delay distributions and their corresponding statistics are evaluated. Extensive Monte Carlo simulations of 5000 runs are performed to generate delay distributions, and mean ($\mu _{\tau ,NAND}$), standard deviation ($\sigma _{\tau ,NAND}$) and Computational Time (CT) are computed. The NMOS stack delay distribution plots generated by the proposed models are superimposed on the SPICE distributions.

Statistics of Delay Distributions with Variability in $\boldsymbol{{V_{th}}}$, $\boldsymbol{{L_{g}}}$, and W

The comparison of model predicted distribution statistics to SPICE simulations for simultaneous variations in ${V_{th}}$, ${L_{g}}$, and W of ±10% each, are summarized in Table 1. The model predicted delay mean error is less than 0.02% for $\tau {_{pHLA}}$, 0.12% for $\tau {_{pHLB}}$, and 0.06% for $\tau {_{pHLAB}}$, respectively, against the SPICE simulated data. As indicated by the standard deviation statistics, the model generated distributions are at least +13.77% tighter than SPICE distributions, demonstrating better delay predictability. Figure 4 compares the analytical model delay distributions of $\tau {_{pHLA}}$, $\tau {_{pHLB}}$, and $\tau {_{pHLAB}}$ with those of SPICE simulations, for simultaneous variations in ${V_{th}}$, ${L_{g}}$, and W of ±10% each.

Fig. 4.

Comparison of SPICE simulated and analytical modeled delay distributions of (A) $\tau {_{pHLA}}$, (B) $\tau {_{pHLB}}$, and (C) $\tau {_{pHLAB}}$ with ±10% $\varDelta {V_{th}}$, $\varDelta {L_{g}}$, and $\varDelta {W}$, and ${V_{DD} = 0.2\,\mathrm{V}}$

Table 2. Delay variability ($\sigma$/$\mu$) statistics for NMOS stack with ${V_{DD} = 0.2 V}$

The error in the analytical model predicted standard deviation, when in error, can be considered to be within an acceptable limit for the 32 nm process, given the high accuracy for the predicted subthreshold mean delay. In contrast to the SPICE simulations, the model generated standard deviation error, in reality, depicts tighter distribution, thereby enhancing predictability and design robustness. Further, a good fit is shown between the model and SPICE generated distributions, thus validating the analytical model approach against SPICE simulations. The results demonstrate that the proposed analytical model is about 70X computationally more efficient than SPICE simulations in generating the delay distributions for all cases. The analytical model approach predicts the delay statistics accurately with significantly less computational complexity.

Delay spread or variability is expressed as the ratio of the standard deviation to the mean, i.e., ($\sigma$/$\mu$). Table 2 shows the variability to be 33.41%, 36.12%, and 34.19% with SPICE simulations and 28.82%, 28.81%, and 28.82% with the model for $\tau {_{pHLA}}$, $\tau {_{pHLB}}$, and $\tau {_{pHLAB}}$, respectively, under ±10% variations in ${V_{th}}$, ${L_{g}}$, and W each. The analytical model based design generates delay distributions tighter than those of SPICE simulations, resulting in better predictability and increased performance gains.

In order to ensure that the proposed model operates over a wide range of supply voltage in the subthreshold regime, the accuracy and efficacy of the models are validated at ${V_{DD}}$ = 0.18 V and ${V_{DD}}$ = 0.23 V. The delay variability statistics of $\tau {_{pHLA}}$, $\tau {_{pHLB}}$, and $\tau {_{pHLAB}}$ for an NMOS stack are reported in Tables 3 and 4 for simultaneous variations in ${V_{th}}$, ${L_{g}}$, and W of ±10% each, at ${V_{DD,min}}$ = 0.18 V and ${V_{DD,max}}$ = 0.23 V, respectively. The worst-case model computed standard deviation statistics of +24.14% depict better predictability. From the statistics, it is evident that the model predicted mean perfectly matches with the SPICE evaluated mean, with tighter model distributions enhancing predictability and computational efficiency.

Table 3. Statistics of $\tau {_{pHL}}$ for ±10% variations in ${V_{th}}, {L_{g}}$, and W for NMOS stack with ${V_{DD}}$ = 0.18 V

Table 4. Statistics of $\tau {_{pHL}}$ for ±10% variations in ${V_{th}}$, ${L_{g}}$, and W for NMOS stack with ${V_{DD}}$ = 0.23 V

3.2 PMOS Stack Delay Distributions for Subthreshold Operation

The nominal delay values of $\tau {_{pLHA}}$, $\tau {_{pLHB}}$, and $\tau {_{pLHAB}}$ evaluated using SPICE simulations are 62.85 ps, 90.93 ps, and 85.31 ps, respectively. The estimated mean ($\mu _{\tau ,NOR}$), standard deviation ($\sigma _{\tau ,NOR}$), and CT are based on the assumption that the device parameter variations follow Gaussian (normal) distribution with ±3$\sigma$ variation of ±10% of their nominal value.

The statistics for rising edge delay distributions are presented in Table 5 for ±10% variations in ${V_{th}}$, ${L_{g}}$, and W, each. The proposed model generated rising edge delay distributions superimposed on those of SPICE distributions of $\tau {_{pLHA}}$, $\tau {_{pLHB}}$, and $\tau {_{pLHAB}}$ for ±10% variations in ${V_{th}}$, ${L_{g}}$, and W each is shown in Fig. 5. From the standard deviation statistics, it is evident that, the distributions get tighter by at least +9.45%. Further, it is demonstrated that the computational overhead of the proposed models is about 300X lower than that of SPICE counterparts.

Table 5. Statistics of $\tau {_{pLH}}$ for ±10% variations in ${V_{th}}$, ${L_{g}}$, and W for PMOS stack with $V_{DD}$ = 0.2 V

Fig. 5.

Comparison of SPICE simulated and analytical modeled delay distributions of (A) $\tau {_{pLHA}}$, (B) $\tau {_{pLHB}}$, and (C) $\tau {_{pLHAB}}$ with ±10% $\varDelta {V_{th}}$, $\varDelta {L_{g}}$, and $\varDelta$W, and $V_{DD}$ = 0.2 V

Table 6 shows delay variability for PMOS stack of 20.99%, 20.85%, and 19.44% for $\tau {_{pLHA}}$, $\tau {_{pLHB}}$, and $\tau {_{pLHAB}}$, respectively, with SPICE simulations and 17.6% with analytical model based design. The distribution tightness offered by the model results in better predictability and sustained performance gains.

To ensure that the proposed model is comprehensive, the PMOS stack model is validated with ${V_{DD}}$ ranging from 0.18 V–0.23 V ($|{V_{th}}|$ = 0.24123 V). The model predicted delay variability statistics match well with the SPICE statistics as reported in Table 7 for ${V_{DD,min}}$ = 0.18 V and Table 8 for ${V_{DD,max}}$ = 0.23 V for ±10% variations in ${V_{th}}, {L_{g}}$, and W each, with significantly higher computational efficiency of around 500X. While the model exhibits tighter distributions by a minimum of +17.60% at ${V_{DD}}$ = 0.18 V, the model distributions are slightly wider, indicating the worst case standard deviation error of −8.29% at ${V_{DD}}$ = 0.23 V.

Table 6. Delay variability ($\sigma$/$\mu$) statistics for PMOS stack with $V_{DD}$ = 0.2 V

Table 7. Statistics of $\tau {_{pLH}}$ for ±10% variations in ${V_{th}}$, ${L_{g}}$, and W for PMOS stack with ${V_{DD}}$ = 0.18 V

Table 8. Statistics of $\tau {_{pLH}}$ for ±10% variations in ${V_{th}}$, ${L_{g}}$, and W for PMOS stack with ${V_{DD}}$ = 0.23 V

4 Conclusions

In the nanoscale regime, the impact of process variability on circuit design is becoming extremely critical to performance estimation and get further accentuated in the subthreshold regime. To mitigate the undesirable effects induced by process variability, analytical delay variability models based on the CV/I metric are proposed in the design phase, to map the variations in device geometry and electrical parameters to the delay variations at the circuit level. To validate the adequacy and scalability of the models with circuit size, analytical models are derived to compute the delay variability of NAND and NOR structures, incorporating the stacking effect. The delay distributions generated by the proposed models in 32 nm PTM technology are superimposed on the distributions generated using the SPICE simulator, and an excellent fit is achieved, thus validating the model’s delay prediction against the SPICE results over a wide range of subthreshold operation. The accuracy, adequacy, and simplicity of the delay variability models offer enhanced predictability and design robustness at the system design level. The proposed delay variability models are about 70X - 500X computationally more faster than SPICE simulations.

Process variation-aware analytical models can be extended to incorporate variations in supply voltage and temperature, demanding equal attention in the design of digital subthreshold circuits, resulting in comprehensive PVT-aware circuit design.