Abstract
This section addresses questions related to the basic language elements of VHDL. It includes discussions on the salient points of concurrent statements, configurations, ports, arithmetic issues, and package Std_Logic_1164. Synthesis is also addressed because of its importance in the design of ASICs and FPGAs.
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© 1997 Springer Science+Business Media New York
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Cohen, B. (1997). Language Elements. In: VHDL Answers to Frequently Asked Questions. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2624-4_1
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DOI: https://doi.org/10.1007/978-1-4757-2624-4_1
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4757-2626-8
Online ISBN: 978-1-4757-2624-4
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