Overview
To achieve a minimum-area layout, circuit interconnections should in general be realized with minimum total wirelength. This chapter discusses the corresponding Steiner minimal tree (SMT) problem, which seeks to connect a given set of points in the plane using the minimum amount of wiring. The SMT problem is central to VLSI global routing and wiring estimation; it also arises in such non-VLSI applications as communication network design. Recent reference books treat the Steiner problem in detail [138, 139]. Thus, in this chapter we will limit our discussion to the rectilinear SMT formulation, which reflects the Manhattan geometry of VLSI layout. The discussion focuses on an iterative construction, called Iterated 1-Steiner, that eschews traditional analogies to minimum spanning tree solutions. Practical implementation issues are discussed as well.
Our development will be as follows. We first demonstrate that many existing SMT heuristics have a performance ratio of 3/2 in the Manhattan plane, which is the same bound achieved by the minimum spanning tree (MST) construction. We then develop the Iterated 1-Steiner (I1S) heuristic, an iterative construction that can achieve good performance even on inputs that are pathological for previous methods. For uniform distributions of 8-point instances in the plane, I1S obtains solution costs that are optimal for 90% of uniformly distributed instances, and average within 0.25% of optimal overall. (The I1S approach also applies to graph instances and higher-dimensional geometric instances.) We present a straightforward implementation of I1S, along with a parallel implementation that achieves near-linear speedup. Similarities between I1S and the recent method of Zelikovsky are also discussed. Finally, we show that any pointset in the Manhattan plane has an MST with maximum degree 4, and that in three-dimensional Manhattan space the maximum MST degree is 14 (the best previous bounds were 6 and 26, respectively): this result improves I1S runtimes and is of independent theoretical interest. The chapter concludes with a discussion of the Steiner problem in graphs.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1995 Springer Science+Business Media New York
About this chapter
Cite this chapter
Kahng, A.B., Robins, G. (1995). Area. In: On Optimal Interconnections for VLSI. The Springer International Series in Engineering and Computer Science, vol 301. Springer, Boston, MA. https://doi.org/10.1007/978-1-4757-2363-2_2
Download citation
DOI: https://doi.org/10.1007/978-1-4757-2363-2_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5145-8
Online ISBN: 978-1-4757-2363-2
eBook Packages: Springer Book Archive