Abstract
The design of embedded Systems-on-Chip (SOC) is influenced by several evolutionary trends, such as the increase in design complexity made possible through shrinking features sizes coupled with larger die sizes for chips. On the other hand, the increasing complexity of building blocks leads to a revolutionary challenge in the emerging system design process that combines complex Intellectual-Property (IP) library blocks to create specialized embedded SOC under tight time-to-market deadlines. Such IP libraries frequently consist of pre-designed mega-cells such as processor cores and memories; several new architectural and optimization issues arise in the process of incorporation of these complex components in application-specific embedded systems. In this book, we described techniques for incorporating memory architectures in such embedded systems that contain both custom-synthesized hardware, as well as programmable processor cores.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 1999 Springer Science+Business Media New York
About this chapter
Cite this chapter
Panda, P.R., Dutt, N., Nicolau, A. (1999). Conclusions. In: Memory Issues in Embedded Systems-on-Chip. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-5107-2_8
Download citation
DOI: https://doi.org/10.1007/978-1-4615-5107-2_8
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-7323-0
Online ISBN: 978-1-4615-5107-2
eBook Packages: Springer Book Archive