Memory Architecture Exploration

Abstract

An important feature of embedded processor-based design for systems-on-chip is that the CPU core is decoupled from the on-chip memory, and it is the system designer’s responsibility to instantiate an appropriate on-chip memory configuration in his design. Traditionally, cache configuration for commercial microprocessors has been determined by conducting experiments on benchmark examples. Since general-purpose microprocessors in a PC or workstation environment have to execute a large variety of application software, a usual and effective means to improve performance has been to increase the cache size to the extent allowable by silicon area constraints. This strategy is acceptable because, in the absence of advance knowledge of the application programs that will execute on the processor, it is fair to assume that an increase in cache size will, in most cases, lead to improvement in performance, because more instruction and data can be held in local memory using larger caches, leading to possibly greater degree of reuse. However, in the embedded processor domain, there is often only a single application, and it is possible to conduct a more thorough analysis of the application to determine the best memory configuration. When coupled with an aggressive compiler that exploits the knowledge of this architecture, the impact on the overall design is significant. For instance, if an analysis of the application reveals that the data cache hit ratio is not likely to improve for cache sizes larger than 1 KByte, the information can be utilized to allocate expensive on-chip silicon area to other hardware resources, instead of an unnecessarily large cache.