Abstract
The response and the characteristics of present models of artificial neural nets are primarily investigated by simulation on vector computers, workstations, special coprocessors or transputer arrays. The fundamental drawback of such simulators is that the spatio-temporal parallelism in the processing of information that is inherent to the neural net is lost entirely or partly and that the computing time of the simulated net especially for large associations of neurons (tailored to application-relevant tasks) grows to such orders of magnitude that a speedy acquisition of “neural” know-how is hindered or made impossible.
This is a preview of subscription content, log in via an institution to check access.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
DARPA Neural Network Study, pp.34 (figure 2.14-15), pp.330 (figure 28.5), AFCEA International Press, Nov. 1988
H.P. Graf, “A Reconfigurable CMOS Neural Network”, Digest of Technical Papers of the Int. Solid State Circuits Conf., vol.33, pp.144, San Francisco, Febr. 1990
J.B. Theeten et al., “The L-Neuro-Chip: A Digital VLSI With On-Chip Learning Mechanism”, Proc. Int. Neural Network Conf., pp. 593–596, Kluwer Academic Publishers, July 1990
D. Hammerstrom, E. Means, “System Design for A Second Generation Neurocomputer”, Proc. IJCNN-90-Wash-DC, vol. II, pp. 80–83, LEA Publishers, Jan. 1990
M. Yasunaga et al., “Design, Fabrication And Evaluation Of A 5-Inch Wafer Scale Neural Network LSI Composed of 576 Digital Neurons”, Proceedings of the IJCNN-90, vol. II, pp. 527–535, San Diego, June 1990
A. Chiang et al., “A Programmable CCD Signal Processor”, Digest of Technical Papers of the Int. Solid State Circuits Conf., vol.33, pp.146, San Francisco, Febr. 1990
M. Holler et al., “An Electrically Trainable Artificial Neural Network (ETANN) with 10240 Floating Gate Synapses”, Proceedings of the IJCNN-89, pp. 11–191, Washington DC, June 1989
H.P. Graf et al.,“VLSI-Implementation of a Neural Network Memory with Several Hundreds of Neurons”, AIP Cof. Proc. Neural Networks for Computing, Snowbird, Utah, 1986
C.A. Mead et al.,“VLSI-Architectures for Implementation of Neural Networks”, California Institute of Technology, Pasadena, USA. AIP Cof. Proc. Neural Networks for Computing, nowbird, Utah, 1986
A.P.Thakoor et al.,“Electronic Neural Network with Optically Modulated Variable Strength. Resistive a-Si:H Interconnects for Analog Computation”, MRS Spring Meeting, paper E 7.5, Reno, Nevada, 1988
E. Vittoz et al., “Analog Storage of Adjustable Synaptic Weights”, 3rd chapter of this book
M. Verleysen, P. Jespers, “Precision Of Computations In Analog Neural Networks, 4th chapter of this book
DARPA Neural Network Study, pp.372 (table 33.1–5), AFCEA International Press, Nov. 1988
J. Harris et al., “Resistive Fuses: Analog Hardware for Detecting Discontinuities in Early Vision”, pp. 27–56, in Analog VLSI Implementation of Neural Systems, edited by C. Mead and M. Ismail, Kluwer Academic Publishers 1989
U. Ramacher, B. Schürmann, “Unified Description of Neural Algorithms For Time-independent Pattern Recognition”, 13th chapter of this book
B. Schürmann, J. Hollatz, U. Ramacher, “Adaptive Recurrent Neural Networks and Dynamic Stability”, in: L. Carrido (ed.), Proc. XI Sitges Conf. on Neural Networks, 1990, Springer, Heidelberg, to appear
S. Y. Kung, J. N. Hwang, “Parallel Architectures for Artificial Neural Nets”, vol.2, IEEE Int. Conf. on Neural Networks, San Diego, July 1988
U. Ramacher, “Systolic Architectures for Fast Emulation of Artificial Neural Networks”, poster paper, presented at IEEE Int. Conf. on Neural Networks, San Diego, July 1988 published in: Proceedings of the Int. Conf. on Systolic Arrays, Killarney, Ireland, Prentice Hall 1989
U. Ramacher et al., “Design of a 1st Generation Neurocomputer”, 14th chapter of this book
A.J. Agranat et al., “A CCD Based Neural Network Integrated Circuit With 64K Analog Programmable Synapses”, Proc. IJCNN-90, vol. 11, pp. 551–555, June 1990
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 1991 Springer Science+Business Media Dordrecht
About this chapter
Cite this chapter
Ramacher, U. (1991). Guide Lines to VLSI Design of Neural Nets. In: Ramacher, U., Rückert, U. (eds) VLSI Design of Neural Networks. The Springer International Series in Engineering and Computer Science, vol 122. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3994-0_1
Download citation
DOI: https://doi.org/10.1007/978-1-4615-3994-0_1
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4613-6785-7
Online ISBN: 978-1-4615-3994-0
eBook Packages: Springer Book Archive