Abstract
This paper describes the design and the implementation of a logic programming language on a massively parallel VLSI architecture in an efficient and scalable way. This implementation is based on the AND/OR Process Model which allows the exploitation of both AND and OR parallelism in logic programs. A distributed memory model is used, and a decentralized control mechanism has been designed. The parallel architecture, which the system is implemented on,consists of a network of Inmos Transputers, the AND/OR processes are implemented as Occam processes mapped onto the Transputer nodes.
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References
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© 1991 Springer Science+Business Media New York
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Cannataro, M., Spezzano, G., Talia, D. (1991). A Multi-Transputer Architecture for a Parallel Logic Machine. In: Delgado-Frias, J.G., Moore, W.R. (eds) VLSI for Artificial Intelligence and Neural Networks. Springer, Boston, MA. https://doi.org/10.1007/978-1-4615-3752-6_16
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DOI: https://doi.org/10.1007/978-1-4615-3752-6_16
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