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Physical Restructuring

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Wafer-Level Integrated Systems

Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 70))

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Abstract

This chapter considers physical alterations of a fabricated integrated circuit to correct for fabrication faults and increase the yield of functional monolithic IC/WSI circuits. The term “physical restructuring” is generally here used to represent physical alteration of the circuit interconnection links, including switches along interconnection paths. The alterations may involve addition or deletion of connections between physical interconnections or physical programming of switches controlling the interconnection paths. Typically, physical restructuring represents post-fabrication processing of the circuitry. Some of the techniques described here (e.g. electrically programmed switches with fuses blown by applying voltages above some threshold) physically alter switching devices without requiring additional fabrication steps and may allow reprogramming of the interconnections.

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References

  1. J. Fried, An analysis of power and clock distribution for WSI systems, in Wafer Scale Integration, G. Saucier and J. Trihle (Eds), pp. 127–137 (1986).

    Google Scholar 

  2. R. M. Lea, A WSI image processing module, in Wafer Scaie Integration, G. Saucier and J. Trihle (Eds), pp. 43–58 (1986).

    Google Scholar 

  3. G. H. Chapman, Laser linking technology for RVLSI, in Wafer-Scale Integration, C. Jesshope and W. Moore (Eds), Adam Hilger Pubs, pp.204–215 (1987).

    Google Scholar 

  4. L. L. Burns, Laser Pantography, in Wafer Scaie Integration, G. Saucier and J. Trihle (Eds), Elsevier Science Press, pp. 281–290 (1986).

    Google Scholar 

  5. J.J. Barrett, E. M. Smith and P. L. Moran, A copper tracking technique for wafer scale integration, in Wafer Scaie Integration, G. Saucier and J. Trihle (Eds), Elsevier Science Press, pp. 291–300 (1986).

    Google Scholar 

  6. G. Nicholas, Technical and economical aspect of laser repair of WSI memory, in Wafer Scaie Integration, G. Saucier and J. Trihle (Eds), Elsevier Science Press, pp. 271–280 (1986).

    Google Scholar 

  7. R. P. Cenker, D. O. Clemons, W. R. Huber, J. B. Petrizzi, F. J. Procyk and G. M. Trout, A fault-tolerant 64K dynamic random access memory, IEEE Trans. Electron Devices, vol. ED-26, pp. 853–860 (1979).

    Article  Google Scholar 

  8. R. T. Smith, J. D. Chlipala, J. F. M. Bindels, R. G. Nelson, F. H. Fischer and T. F. Mantz., Laser programmable redundancy and yield improvement in a 64K DRAM, IEEE J. Solid-State Circuits, vol. SC-16, pp. 506–514 (1981).

    Article  Google Scholar 

  9. B. F. Fitzgerald and E. P. Thoma, Circuit implementation of fusible redundant addresses of RAMs for productivity enhancement, IBM J. Res. Develop., vol. 24, pp. 291–298 (1980).

    Article  Google Scholar 

  10. C.-W. Chen, J.-P. Peng, M.-Y. S. Shyu, M. Amundson and J. C. Yu, A fast 32K x 8 CMOS static RAM with address transition detection, IEEE J. Solid-State Circuits, vol. SC-22, pp. 533–537 (1987).

    Article  Google Scholar 

  11. S. Asai, Semiconductor memory trends, Proc. IEEE, vol. 74, pp. 1623–1635 (1986).

    Article  Google Scholar 

  12. News Item, Polysilicon lines made with laser, Semiconductor International, pg. 16, (Sept. 1984).

    Google Scholar 

  13. H. Stopper, A wafer with electrically programmable interconnections, Digest: IEEE Int. Solid-State Circuits Conf., pp. 268–269 (1985).

    Google Scholar 

  14. R. Braun and S. Sharp, How to use silicon circuit boards effectively, Hybrid Circuit Technology, pp. 55–60, (Sept. 1987).

    Google Scholar 

  15. M. J. Mayo, Photodeposition: enhancement of deposition reactions by heat and light, Solid State Technology, pp. 141–144 (April 1986).

    Google Scholar 

  16. R. T. Young, J. Narayan, W. H. Christie, G. A. van der Leeden, J. I. Levatter and L. J. Cheng, Semiconductor processing with excimer lasers, Solid State Technology, pp. 183–188 (Nov. 1983).

    Google Scholar 

  17. T. McGrath, Applications of excimer lasers in microelectronics, Solid State Technology, pp. 165–169 (Dec. 1983).

    Google Scholar 

  18. R. Solanki, C. A. Moore and G. J. Collins, Laser-induced chemical vapor deposition, Solid State Technology, pp. 220–227 (June 1985).

    Google Scholar 

  19. T. T. Orlowski and H. Richter, Ultrafast laser-induced oxidation of silicon: a new approach towards high quality, low temperature, patterned SiO 2 formation, Appl. Phys. Lett., vol. 45, pp. 241–243 (1984).

    Article  Google Scholar 

  20. D. J. Ehrlich, R. M. Osgood Jr., and T. F. Deutsch, Photodeposition of metal films with ultraviolet laser light, J. Vac. Sci. Technol., vol. 21, pp. 23–32 (1982).

    Article  Google Scholar 

  21. J. Y. Tsao, D. J. Ehrlich, D. J. Silversmith and R. W. Mountain, Direct-write metalization of silicon MOSFET’s using laser photodeposition, IEEE Electron Dev. Lett., vol. EDL-3, pp. 164–166 (1982).

    Article  Google Scholar 

  22. D. Bauerle, P. Irstgler, G. Leyendecker, H. Noll and D. Wagner, Ar + laser induced chemical vapor deposition of Si from SiH 4 , Appl. Phys. Lett., vol. 40, pp. 819–821 (1982).

    Article  Google Scholar 

  23. D. J. Ehrlich, R. M. Osgood Jr. and T. F. Deutsch, Laser microreaction for deposition of doped silicon films, Appl. Phys. Lett., vol. 39, pp. 957–959 (1981).

    Article  Google Scholar 

  24. C. P. Christenson and K. M. Lakin, Chemical vapor deposition of silicon using a CO 2 laser, Appl. Phys. Lett., vol. 32, pp. 254–256 (1978).

    Article  Google Scholar 

  25. D. C. Shaver, R. W. Mountain and D. J. Silversmith, Electron-beam programmable 128-Kbit wafer-scale EPROM, IEEE Electron Dev. Lett., vol. EDL-4, pp. 153–155 (1983)

    Article  Google Scholar 

  26. P. W. Cook, S. E. Schuster and R. J. von Gutfeld, Appl. Phys. Lett, vol. 26, pp. 124 (1975)

    Article  Google Scholar 

  27. Y. C. Kiang, J. R. Moulic, W.-K. Chil and A. C. Yen, Modification of semiconductor device characteristics by lasers, IBM J. Res. Dev., vol. 26, pp. 171–176 (1982).

    Article  Google Scholar 

  28. J. A. Yasaitis, G. H. Chapman and J. I. Raffel, IEEE. Electron Dev. Lett., vol. EDL-3, pp. 184-? (1982).

    Article  Google Scholar 

  29. J. Y. Tsao and D. H. Ehrlich, UV laser photopolymerization of volatile surfaceabsorbed methyl methacrytate, Appl. Phys. Lett., vol. 42, pp. 997–999 (1983).

    Article  Google Scholar 

  30. News item, Semiconductor International, p. 30 (Aug 1986).

    Google Scholar 

  31. D. J. Ehrlich, J. Y. Tsao, D. J. Silversmith, J. H. C. Sedlacek, R. W. Mountain and W. S. Graber, Laser microchemical techniques for reversible restructuring of gate-array prototypes, IEEE Electron Dev. Lett., vol. EDL-5, pp. 32–35 (1984).

    Article  Google Scholar 

  32. J. Y. Tsao and D. J. Ehrlich, Laser controlled etching of aluminum, Appl. Phys. Lett., vol. 43, pp. 146–148 (1983).

    Article  Google Scholar 

  33. J. G. Black, D. J. Ehrlich, J. H. C. Sedlacek, A. D. Feinerman and H. H. Busta, Rapid low-resistance interconnects by selective tungston deposition on laser-direct-written polysilicon, IEEE Electron Dev. Lett., vol. EDL-7, pp. 422–424 (1986).

    Article  Google Scholar 

  34. S. Somekh, Introduction to ion and plasma etching, J. Vac. Sci. Technol., vol. 13, pp. 1003–1007 (1976).

    Article  Google Scholar 

  35. R. L. Kubena, R. L. Seliger and E. H. Stevens, High resolution sputtering using a focussed ion beam, Thin Solid Films, vol. 92, pp. 165–169 (1982)

    Article  Google Scholar 

  36. H. Yamaguchi, A. Shimase, S. Haraichi and T. Miyauchi, Characteristics of silicon removal by fine focussed gallium ion beams, J. Vac. Sci. Technol. B, vol. 3, pp. 71–74 (1985).

    Article  Google Scholar 

  37. H. Morimoto, Y. Sasaki, Y. Watakabe and T. Kato, Characteristics of submicron patterns fabricated by gallium focussed-ion-beam sputtering, J. Appl. Phys., vol. 57, pp. 159–160 (1985).

    Article  Google Scholar 

  38. L. R. Harriott, A. Wagner and F. Fritz, Integrated circuit repair using focussed ion beam milling, J. Vac. Sci. Technol. B, vol. 4, pp. 181 (1986).

    Article  Google Scholar 

  39. J. Melngailis, C. R. Musil, E. H. Stevens, M. Utlaut, E. M. Kellog, R. T. Post, M. W. Geis and R. W. Mountain, The focussed ion beam as an integrated circuit restructuring tool, J. Vac. Sci. Technol. B, vol. 4, pp. 176 (1986).

    Article  Google Scholar 

  40. T. Ishitani, Y. Kawanami and H. Todokoro, Aluminum-line cutting end monitor using scanning-ion-microscope voltage contrast images, Japan J. Appl. Phys., vol. 24, pp. L133-L134 (1985).

    Article  Google Scholar 

  41. V. Wang, J. W. Ward and R. L. Seliger, A mass-separating focussed-ion~beam system for maskless ion implantation, J. Vac. Sci. Technol., vol. 19, pp1158–1163 (1981).

    Article  Google Scholar 

  42. R. L. Kubena, C. L. Anderson, R. L. Seliger, R. A. Juliens, E. H. Stevens, I. Lagnado, FET fabrication using maskless ion implantation, J. Vac. Sci. Technol., vol. 19, pp. 916–920, (1981).

    Article  Google Scholar 

  43. A. Wagner, Applications of focused ion beams to microlithography, Solid State Technology, pp. 97–103 (May 1983).

    Google Scholar 

  44. D. C. Shaver and B. W. Ward, Integrated circuit diagnosis using focussed ion beams, J. Vac. Sci. Technol. B, vol. 4, pp. 185 (1986).

    Article  Google Scholar 

  45. J. Melngailis, Focussed ion beam technology and applications, J. Vac. Sci. Technol. B, vol. 5, pp. 469–495 (1987).

    Article  Google Scholar 

  46. T. Shiokawa, P. H. Kim, K. Toyoda and S. Namba, T. Namba, T. Matsui and K. Gamo 100 kev focussed ion beam system with E × B mass filter for maskless ion implantation, J. Vac. Sci. Technol.B, vol. 1, pp. 1117 (1983).

    Article  Google Scholar 

  47. J.J. Muray, Physics of ion beam wafer processing, Semiconductor International, pp. 130–135 (April 1984).

    Google Scholar 

  48. D. C. Shaver and B. W. Ward, Semiconductor applications of focussed ion beam micromachining, Solid State Technology, pp. 73–78 (Dec 1985).

    Google Scholar 

  49. C. R. Musil, J. L. Bartlet and J. Melngailis, Focussed ion beam microsurgery for electronics, IEEE Electron Device Lett., vol. EDL-7, pp. 285–287 (1986).

    Article  Google Scholar 

  50. D. R. Herriot, Electron-beam lithography machines, in Electron-Beam Technology in Microelectronic Fabrication, G. R. Brewer (Ed.), Academic Press, New York (1980).

    Google Scholar 

  51. D. R. Herriot, R. J. Collier, D. S. Alles and J. W Stafford, EBES: a practical electron lithographic system, IEEE Trans. Electron Dev., vol. ED-22, pp. 385–392 (1975)

    Article  Google Scholar 

  52. J. L. Freyer and K. P. Standiford, Design of an accurate production e-beam system, Solid State Technology, pp. 165–170 (Sept. 1983).

    Google Scholar 

  53. R. M. Sills and K. P. Standiford, E-beam system metrology, Solid State Technology, pp. 191–196 (Sept. 1983).

    Google Scholar 

  54. Y. Tarui (ed.), VLSI Technology: Fundamentals and Applications, Springer-Verlag, New York (1986). Chapter 2.

    Google Scholar 

  55. I. Brodie and J. M. Muray, The Physics of Micro fabrication, pp. 316–329, Plenum Press, New York (1982).

    Google Scholar 

  56. P. Petric and O. Woodward, Direct-write electron beam systems, Solid State Technology, pp 154–160 (Sept 1983).

    Google Scholar 

  57. S. J. Gillespie, Top-edge imaging in e-beam lithography, Solid State Technology, vol. 174–176 (Sept 1983).

    Google Scholar 

  58. R. D. Moore, EL systems: high throughput electron beam lithography tools, Solid State Technology, pp. 127–132 (Sept 1983).

    Google Scholar 

  59. W. R. Livesay, J. S. Greeneich, J. E. Wolfe and R. J. Felker, A processcompatible electron beam direct write system, Solid State Technology, pp. 137–139 (Sept 1983).

    Google Scholar 

  60. P. Girard, B. Pistoulet, M. Valenza and R. Lorival, Electron beam switching of floating gate MOS transistors, IFIP Int. Workshop on Wafer Scale Int., Brunei University, (Sept. 23–25, 1987).

    Google Scholar 

  61. P. Girard, F. M. Roche and B. Pistoulet, Electron beam effects on VLSI MOS: conditions for testing and reconfiguration, in Wafer-Scale Integration, G. Saucier and J. Tritile (Eds.), North-Holland, Amsterdam, The Netherlands, pp. 301–310 (1986).

    Google Scholar 

  62. D. C. Shaver, Proc. 2nd CALTECH conference on VLSI, pp. 111, California Inst. Technol., Pasadena, CA (Jan. 1981).

    Google Scholar 

  63. D. C. Shaver, Electron-beam technique for integrated circuit testing and customization, Proc. IEEE Custom Integrated Circuits Conf., pp. 606–609 (May 1984).

    Google Scholar 

  64. S. L. Garverick and E. A. Pierce, A single wafer 16-point 16 MHz FFT processor, Proc. IEEE Custom Integrated Circuits Conf., pp. 344–348 (May 1983).

    Google Scholar 

  65. F. M. Rhodes, Applications of RVLSI to signal processing, in Wafer Scale Integration, C. Jesshope and W. Moore (eds.), Adam Hilger Pubs., Bristol, pp. 223–235 (1986).

    Google Scholar 

  66. J. J. Dituri et al., Hough transform system, Proc. 1986 Workshop on VLSI Signal Processing, U. Southern California (Nov. 1986).

    Google Scholar 

  67. G. H. Chapman, J. I. Raffel, J. M. Canter and F. M. Rhodes, Advances in laser link technology for wafer-scale circuits, IFIP Int. Workshop on Wafer-Scale Integration, Sept. 23–25, 1987, Brunei University.

    Google Scholar 

  68. J. R. Mann and F. M. Rhodes, A wafer scale DTW multiprocessor, Proc. IEEE Int. Conf. Acoustics, Speech and Signal Processing, pp. 1557–1560 (April 1986).

    Google Scholar 

  69. J. I. Raffel, A. H. Anderson, G. H. Chapman, K. H. Konkile, B. Mathur, A. M. Soares and P. W. Wyatt, A wafer-scale integrator, Proc. IEEE Int. Conf. Computer Design, pp. 121–126 (Oct. 1984).

    Google Scholar 

  70. J. I. Raffel, M. L. Naiman, R. L. Burke, G. H. Chapman and P. G. Gottschalk, Laser programmed vias for resiruciurable VLSI, Digest: IEEE Int. Device Meeting, pp. 132–135 (1980).

    Google Scholar 

  71. G. H. Chapman J. I. Raffel, J. A. Yasaitis and S. M. Cheston, A laser linking process for resiruciurable VLSI, Digest: OSA/IEEE Conf. on Lasers and Electrooptics, pp. 60, 62–63 (1982).

    Google Scholar 

  72. J. I. Raffel et al., On the use of nonvolatile programmable links for resiruciurable VLSI, Proc. 1979 Caltech Conf. on VLSI, pp. 95–104 (1979).

    Google Scholar 

  73. G. H. Chapman and J. A. Burns, Enhanced operation of wafer-scale circuiis using nitride α-Si laser links, Digest: OSA/IEEE Conf. on Lasers and Electrooptics, pg. 148 (1986).

    Google Scholar 

  74. J. M. Canter, G. H. Chapman, B. Mathur, M. L. Naiman and J. I. Raffel, A laser-induced ohmic link for wafer-scale integration, IEEE Trans. Electron Devices, vol. ED-33, pp. 1861 (1986).

    Article  Google Scholar 

  75. Restructurable VLSI Program: Semiannual Technical Summary, Lincoln Laboratories Technical Report (March 1985).

    Google Scholar 

  76. Restructurable VLSI Program: Semiannual Technical Summary, Lincoln Laboratories Technical Report (Sept. 1985).

    Google Scholar 

  77. B. J. Donlan and J. F. McDonald, A placement and routing system for wafer scale, Proc. IEEE Int. Conf. on Computer-Aided Design, pp. 462–464 (1986).

    Google Scholar 

  78. N. R. Quinn and M. A. Breuer, A force directed placement procedure for printed circuit boards, IEEE Trans. Circuits and Systems, vol. 26, pp. 377–388 (1979).

    Article  MATH  Google Scholar 

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  1. AT&T Bell Laboratories, USA

    Stuart K. Tewksbury

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© 1989 Kluwer Academic Publishers

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Tewksbury, S.K. (1989). Physical Restructuring. In: Wafer-Level Integrated Systems. The Kluwer International Series in Engineering and Computer Science, vol 70. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1625-1_9

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  • DOI: https://doi.org/10.1007/978-1-4613-1625-1_9

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