Abstract
The previous chapter emphasized general purpose testing schemes for combinational and sequential logic circuits. This chapter describes several special-purpose testing schemes. Three distinct circuit functions (memory arrays, regular logic arrays and programmable logic arrays) are used as examples of the various techniques which can be used. A major issue for special purpose testing is reduction of the size of the set of test vectors, drawing on the structure of the specific function being considered. Similar reductions in the size of tests for wafer-scale integrated circuits will also be important and the commonly used regularity of such wafer-scale functions suggests that distributed testing, conducted in parallel on regions of the array which do not interact through faults, will be possible. Given the set of test vectors, and regions which can be concurrently tested, the actual generation, routing and response analysis of test vectors can be implemented using the general purpose testing structures (e.g. scan path testing, response compression, TMR, etc.) discussed in the previous chapter. The techniques discussed below begin with testing of memory arrays, where the contents of each individual cell (storage site) can be directly viewed at the memory array’s primary output. Next, testing of regular logic arrays is considered. In this case, the regular structure is qualitatively similar to that of the memory array but the responses of internal cells (e.g. accumulator cells) are not directly observable at the array’s primary outputs. Design of the test must then propagate those responses, without modification, through the array to the primary outputs.
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References
N. Kanopoulos and G. T. Mitchell, Design for testability and self-testing approaches for bit-serial signal processors, IEEE Design and Test, pp. 52–59 (May 1984).
Y. Kitano, S. Kohda, H. Kikuchi and S. Sakai, A 4-Mbit full wafer ROM, IEEE J. Solid-State Circuits, vol. SC-15, pp. 686–693 (1980).
Y. Egawa, T. Wada, Y. Ohmori, N. Tsuda and K. Masuda, A 1-Mbit full wafer MOS RAM, IEEE J. Solid-State Circuits, vol. SC-15, pp. 677–686 (1980).
S. Kohda, K. Masuda, K. Matsuzawa and Y. Kitano, A giant chip multigate transistor ROM circuit design, IEEE J. Solid-State Circuits, vol. SC-21, pp. 713–719 (1986).
J.-M. Pernot and J. Le Ber, Wafer scale memory, in Wafer Scale Integration, G. Saucier and J. Tritile (Eds), Elsevier Science Pubs., pp. 94–114 (1986).
D. Pountain, Integration on a new scale, BYTE, pp. 351–356 (Nov. 1986).
L. Bentley and C. R. Jesshope, The implementation of a two-dimensional redundancy scheme in a wafer scale high-speed disk memory, in Wafer Scaie Integration, C. Jesshope and W. Moore (Eds), Adam Hilger, Bristol, pp. 187–197 (1986).
S. K. Jain and C. E. Stroud, Built-in self-testing of embedded memories, IEEE Design and Test, vol. 3, pp. 27–37 (1986).
J. Guilford and E. H. Rogers, Design of the WARP machine, a wafer scale database system, Proc. IEEE Int. Conf. Computer Design, pp. 655–659 (1985).
K. Kinoshita and K. K. Saluja, Built-in testing of memory using an on-chip compact testing scheme, IEEE Trans. Computers, vol. C-35, pp. 862–870 (1986).
K. K. Saluja, S. H. Sng and K. Kinoshita, Built-in self-testing RAM: a practical alternative, IEEE Design and Test, pp. 42–51 (Feb 1987).
Y. You and J. P. Hayes, A self-testing dynamic RAM chip, IEEE J. Solid-State Circuits, vol. SC-20, pp. 428–435 (1985).
J. P. Hayes, Design of self-testing VLSI components, Proc. IEEE CompEuro, pp. 56–59 (1987).
O. Kowarik, R. Kraus and K. Hoffmann, Self-repairing semiconductor memories, Proc. IEEE CompEuro, pp. 656–659 (1987).
J. P. Hayes, Testing memories for single cell, pattern-sensitive faults, IEEE Trans. Computers, vol. C-29, pp. 249–254 (1980).
D. S. Suk and S. M. Reddy, Test procedures for a class of pattern-sensitive faults in semiconductor random-access memories, IEEE Trans. Computers, vol. C-29, pp. 419–429 (1980).
R. Nair, S. M. Thatte and J. A. Abraham, Efficient algorithms for testing semiconductor random-access memories, IEEE Trans. Computers, vol. C-27, pp. 572–576 (1978).
J. Knaizuk and C. R. P. Hartman, An optimal algorithm for testing stuckat faults in random access memories, IEEE Trans Computers, vol. C-26, pp. 1141–1144 (Nov. 1977).
P. Lechner, W. Mohr and A. Papp, Holding time distribution in dynamic MOS RAMs, Int. J. Electronics, vol. 61, pp. 543–553 (1986).
J. P. Hayes, Detection of pattern sensitive faults in random-access memories, IEEE Trans. Computers, vol. C-24, pp. 150–157 (1975)
V. P. Srini, API tests for RAM chips, IEEE Computer, vol. 10, pp. 32–36 (1977).
S. C. Seth and K. Narayanswamy, A graph model for pattern-sensitive faults in random-access memories, IEEE Trans. Computers, vol. C-30, pp. 973–977 (1981).
C. A. Papachristou and N. B. Sahgal, An improved method for detecting functional faults in semiconductor random access memories, IEEE Trans. Computers, vol. C-34, pp. 110–116 (1985).
Z. Sun and L.-T. Wang, Self-testing of embedded RAMs, Proc. IEEE Int. Test Conf., pp. 148–156 (1984).
M. S. Abadir and H. K. Reghbati, Functional testing of semiconductor random access memories, ACM Computing Surveys, vol. 15, pp. 175–198 (1983).
M. A. Breuer and A. D. Friedman, Diagnosis and Reliable Design of Digital Systems, pp. 139–170, Computer Science Press, Rockville, MD (1976).
S. M. Thatte, Fault diagnosis and semiconductor random access memories, Techn. Report R-769, Coord. Sci Laboratory, University of Illinois (1977).
D. S. Suk and S. M. Reddy, A march test for functional faults in semiconductor random access memories, IEEE Trans. Computers, vol. C-30, pp. 982–985 (1981).
P. Mazumder, J. H. Patel and W. K. Fuchs, Design and algorithms for parallel testing of random access and content addressable memories, Proc. 24th ACM/IEEE Design Automation Conf., pp. 688–694 (1987).
A. K. Somani, Distributed diagnosis algorithms for large scale regular interconnected structures, Proc. IEEE Int. Conf. on Computers and Applications, pp. 661–666 (1981).
F. P. Preparata, G. Metze and R. T. Chien, On the connection assignment problem of diagnosable systems, IEEE Trans. Electronic Computers, vol. EC-16, pp. 848–854 (1967)
A. K. Somani and V. K. Agarwal, System-level diagnosis in systolic systems, Proc. IEEE Int. Conf. Computer Design, pp. 445–450 (1984).
A. Khurshid and P. D. Fisher, Design of a reconfigurable systolic array using LSSD techniques, Proc. IEEE Int. Conf. Computer Design, pp. 171–175 (1984).
Y.-H. Choi, S. H. Han and M. Malek, Fault diagnosis of reconfigurable systolic arrays, Proc. IEEE Int. Conf. Computer Design, pp. 451–455 (1984).
J.-H. Kim and S. M. Reddy, A fault-tolerant systolic array design using TMR method, Proc. IEEE Int. Conf. Computer Design, pp. 769–773 (1985).
C.-Y. Chen and J. A. Abraham, On the design of fault-tolerant systolic arrays with linear cells, Proc. IEEE Fall Joint Comp Conf., pp. 400–409 (1986).
E. M. Aboulhamid and E. Cerny, Built-in testing of one-dimensional unilateral iterative arrays, IEEE Trans. Computers, vol. C-33, pp. 560–564 (1984).
F. J. O. Dias, Truth-table verification of an iterative logic array, IEEE Trans. Computers, vol. C-25, pp. 605–613 (1976).
A. D. Friedman, Easily testable iterative systems, IEEE Trans. Computers, vol. C-22, pp. 1061–1064 (1973).
R. Parthasarathy and S. M. Reddy, A testable design of iterative logic arrays, IEEE Trans. Circuits and Systems, vol. CAS-28, pp. 1037–1045 (1981).
T. Sridhar and J. P. Hayes, A functional approach to testing bit-sliced microprocessors, IEEE Trans. Computers, vol. C-30, pp. 563–571 (1981).
T. Sridhar and J. P. Hayes, Design of easily testable bit-sliced systems, IEEE Trans. Computers, vol. C-30, pp. 842–854 (1981).
A. L. Rosenberg, The Diogenes approach to testable fault-tolerant arrays of processors, IEEE Trans. Computers, vol. C-32, pp. 902–910 (1983).
J. P. Shen and F. Joel Ferguson, The design of easily testable VLSI array multipliers, IEEE Trans. Computers, vol. C-33, pp. 554–560 (1984).
J. K. Patel and L. Y Fung, Concurrent error detection in ALU’s by recomputing with shifted operands, IEEE Trans. Computers, vol. C-31, pp. 589–595 (1982).
T. Sridhar and J. P. Hayes, Testing bit-sliced system microprocessors, Proc. IEEE Int. Symp. Fault-Tolerant Computing, pp. 211–218 (1979).
K.-H. Huang and J. A. Abraham, Algorithm-based fault tolerance for matrix operations, IEEE Trans. Computers, vol. C-33, pp. 518–528 (1984).
V. S. S. Nair and J. A. Abraham, Average checksum codes for fault-tolerant matrix operations on processor arrays, Proc. Int. Conf. Supercomputing (1987).
J.-Y. Jou and J. A. Abraham, Fault-tolerant matrix arithmetic and signal processing on highly concurrent computing structures, Proc. IEEE, pp. 732–741 (1986).
J.-Y. Jou and J. A. Abraham, Fault-tolerant FFT networks, IEEE Trans. Computers, vol. C-35, pp. 548–561 (1988).
J. A. Abraham, P. Banerjee, C.-Y. Chen, W. K. Fuchs, S.-Y. Kuo and A. L. N. Reddy, Fault-tolerant techniques for systolic arrays, IEEE Computer, pp. 65–75 (July 1987).
S. Bozorgui-Nesbat and E. J. McCluskey, Lower overhead design for testability of programmable logic arrays, IEEE Trans. Computers, vol. C-35, pp. 379–383 (1986).
S. J. Hong, R. G. Gain and D. L. Ostapko, MINI: a heuristic approach for logic minimization, IBM J. Res. Dev., vol. 18, pp. 443–458 (1974).
Y. Kambayashi, Logic design of programmable logic arrays, IEEE IVans. Computers, vol. C-28, pp. 609–617 (1979).
G. D. Hachtel, A. R. Newton and A. L. Sangiovanni-Vincentelli, An algorithm for optimal PLA folding, IEEE Trans. Comp. Aided Design, vol. CAD-1, pp. 63–77 (1982).
R. A. Wood, A high density programmable logic array chip, IEEE Trans. Computers, vol. C-28, pp. 602–608 (1979).
F. Somenzi and S. Gai, Fault detection in programmable logic arrays, Proc. IEEE, vol. 74, pp. 655–668 (1986).
D. K. Pradhan and K. Son, The effect of undetectable faults in PLA ’s and a design for testability, Proc. IEEE Int. Test Conf., pp. 359–367 (1980).
K. S. Ramanatha and N. N. Biswas, A design for testability of undetectable crosspoint faults in programmable logic arrays, IEEE Trans. Computers, vol. C-32, pp. 551–557 (1983).
H. K. Reghbati, Fault detection in PLA’s, IEEE Design and Test, vol. 3, pp. 43–50 (1986).
H. Fujiwara and K. Kinoshita, A design of programmable logic arrays with universal tests, IEEE Trans. Computers, vol. C-30, pp. 823–828 (1981).
R. Treuer, H. Fujiwara and V. K Agarwal, Implementing a built-in self-test PLA design, IEEE Design and Test, pp. 37–48 (Feb 1985).
J. Khakbaz, A testable PLA design with low overhead and high fault coverage, IEEE Trans. Computers, vol. C-33, pp. 743–745 (1984).
N. N. Biswas and J. Jacobs, A testable PLA design with minimal hardware and test set, Proc. IEEE Int. Test Conf., pp. 583–588 (Nov 1985).
V. K. Agarwal, Multiple fault detection in programmable logic arrays, IEEE Trans. Computers, vol. C-29, pp. 518–522 (1980).
E. B. Eichelberger and E. Lindbloom, A heuristic test-pattern generation for programmable logic arrays, IBM J. Res. Dev., vol. 24, pp. 15–22 (1980).
D. L. Ostapko and S. J. Hong, Fault analysis and test generation for programmable logic arrays (PLA’s), IEEE Trans. Computers, vol. C-28, pp. 617–626 (1979).
J. Rajski and J. Tyszer, Combinational approach to multiple contact fault coverage in programmable logic arrays, IEEE Trans. Computers, vol. C-34, pp. 549–553 (1985).
R. S. Wei and A. Sangiovanni-Vincentelli, PLATYPUS: a PLA test generation tool, Proc. IEEE Design Automation Conf., pp. 197–203 (June 1985).
K. A. Hua, J. Y. Jou and J. A. Abraham, Built-in tests for VLSI finite state machines, Proc. IEEE Symp. Fault-Tolerant Computing, pp. 292–297 (1984).
S. Z. Hassan and E. J. McCluskey, Testing PLA’s using multiple signature analyzers, Proc. IEEE Symp. Fault-Tolerant Computing, pp. 422–425 (1983).
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© 1989 Kluwer Academic Publishers
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Tewksbury, S.K. (1989). Function-Specific Testing. In: Wafer-Level Integrated Systems. The Kluwer International Series in Engineering and Computer Science, vol 70. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1625-1_8
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DOI: https://doi.org/10.1007/978-1-4613-1625-1_8
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