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General Testing Techniques

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Wafer-Level Integrated Systems

Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 70))

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Abstract

In this chapter, techniques to generate test stimuli, apply those test to circuit functions and to evaluate the test results [1,2,3,4] are reviewed. The emphasis is on general purpose schemes, such as scan path design of VLSI circuits and syndrome test compression. Special purpose testing schemes (e.g. [5,6,7,8]) developed for specific system functions (PLA’s, random access memories, linear matrix operations, etc) are considered separately in the next chapter.

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References

  1. P. K. Lala, Fault Tolerant and Fault Testable Hardware Design, Prentice-Hall International, Inc., London, England (1985).

    Google Scholar 

  2. E. J. McCluskey, Logic Design Principles with Emphasis on Testable Semicustom Circuits, Prentice-Hall, Englewood Cliffs, NJ (1986).

    Google Scholar 

  3. D. P. Siewiorek and R. S. Swartz, The Theory and Practice of Reliable System Design, Digital Press, Bedford, MA (1982).

    Google Scholar 

  4. J. P. Roth, Diagnosis of automata failure: a calculus and a method, IBM J. Res. Develop., pp. 278–281 (1966).

    Google Scholar 

  5. J. P. Shen and F. J. Ferguson, The design of easily testable VLSI multipliers, IEEE Trans. Computers, vol. C-33, pp. 554–560 (1984).

    Article  Google Scholar 

  6. A. D. Friedman, Easily testable iterative systems, IEEE Trans. Computers, vol. C-22, pp. 1061–1064 (1973).

    Article  Google Scholar 

  7. H. K. Reghbati, Fault detection in PLAs, IEEE Design and Test, pp. 43–50 (Dec 1986).

    Google Scholar 

  8. W. K. Fuchs, C.-Y. R. Chen and J. A. Abraham, Concurrent error detection in highly structured logic arrays, IEEE J. Solid-State Circuits, vol. SC-22, pp. 583–594 (1987).

    Article  Google Scholar 

  9. R. Garcia, The Fairchild Sentry 50 tester: establishing new ATE performance limits, IEEE Design and Test, pp. 101–109 (1984).

    Google Scholar 

  10. T. W. Williams and K. P. Parker, Design for testability — a survey, Proc. IEEE, vol. 71, pp. 98–112 (1983).

    Article  Google Scholar 

  11. E. J. McCluskey, Design for testability, in Recent Developments in Fault Tolerant Computing, D. K. Pradhan (Ed), Prentice-Hall, Englewood Cliffs, NJ (1984).

    Google Scholar 

  12. E. J. McCluskey, A survey of design for testability, VLSI Design, pp. 38–61 (Dec 1984).

    Google Scholar 

  13. R. G. Bennetts, Design for Testable Logic Circuits, Addison-Wesley, London (1984).

    Google Scholar 

  14. B. Konemann, J. Mucha and G. Zwiehoff, Built-in logic block observation techniques, Proc. IEEE Int. Test Conf., pp. 37–41 (1979).

    Google Scholar 

  15. A. Motohara and H. Fujiwara, Design for testability for complete test coverage, IEEE Design and Test, pp. 25–32 (Nov 1984).

    Google Scholar 

  16. M.T.M.R. Segers, The impact of testing on VLSI design methods, IEEE J. Solid-State Circuits, vol. SC-17, pp. 481–486 (1982).

    Article  Google Scholar 

  17. K. A. E. Totton, Review of built-in test methodologies for gate arrays, IEE Proc., vol. 132 (Part E), pp. 121–129 (1985).

    Google Scholar 

  18. C. Jay, J. P. Eynard and G. Saucier, Test facilities and test plans in WSI 2-D arrays, in Wafer Scaie Integration, G. Saucier and J. Trihle (Eds), Elsevier Scientific Pub., pp. 145–167 (1986).

    Google Scholar 

  19. K. Saluja, S. H. Sng and K. Kinoshita, Built-in self-testing RAM: a practical alternative, IEEE Design and Test, pp. 42–51 (Feb 1987).

    Google Scholar 

  20. E. J. McCluskey, Built-in self-test structures, IEEE Design and Test, pp. 29–36 (Apr 1985).

    Google Scholar 

  21. E. J. McCluskey, Built-in self-test techniques, IEEE Design and Test, pp. 21–28 (Apr 1985).

    Google Scholar 

  22. N. Gaitanis and C. Halatsis, A new design method for m-out-of-n TSC checkers, IEEE Trans. Computers, vol. C-32, pp. 273–283 (1983).

    Article  Google Scholar 

  23. J. E. Smith and P. Lam, A theory of totally self-checking system design, IEEE Trans. Computers, vol. C-32, pp. 831–844 (1983).

    Article  Google Scholar 

  24. R. R. Davidson, M. L. Harrison and R. L. Wadsack, BELLMAC-32: a testable 32 bit microprocessor, Proc. IEEE Int. Test Conf., pp. 15–20 (Oct. 1981).

    Google Scholar 

  25. Y. Tamir and C. H. Sequin, Self-checking VLSI building blocks for fault-tolerant multicomputers, Proc. IEEE Int. Conf. Computer Design, pp. 561–564 (Nov. 1983).

    Google Scholar 

  26. Y. Tamir and C. H. Sequin, Design and application of self-testing comparators implemented with MOS PLA’s, IEEE Trans. Computers, vol. C-33, pp. 493–506 (1984).

    Article  Google Scholar 

  27. M. S. Abadir and H. K. Reghbati, Functional testing of semiconductor random access memories, ACM Computing Surveys, vol. 15, pp. 175–198 (1983).

    Article  Google Scholar 

  28. T. Ohsawa, T. Furuyama, Y. Watanabe, H. Tanaka, N. Kushiyama, K. Tsuchida, Y. Nagahama, S. Yamano, T. Tanaka, S. Shinozaki and K. Natori, A 60-ns 4-Mbit CMOS DRAM with build-in self-test function, IEEE J. Solid-State Circuits, vol. SC-22, pp. 663–667 (1987).

    Article  Google Scholar 

  29. M. A. Bayoumi and J. C. H. Yang, A fault-tolerant testable module for waferscale integrated systems, Proc. IEEE CompEuro, pp. 590–593 (1987).

    Google Scholar 

  30. F. J. Mac Williams and N. J. A. Sloane, Pseudo-random sequences and arrays, Proc. IEEE, vol. 64, pp. 1715–1729 (1976).

    Article  MathSciNet  Google Scholar 

  31. C. L. Chen and M. Y. Hsiao, Error-correcting codes for semiconductor memory applications — a state of the art review, IBM J. Res. and Develop., vol. 28, pp. 124–134 (1984).

    Article  Google Scholar 

  32. G. R. Redinbo, Fault-tolerant decoders for cyclic error-correcting codes, IEEE Trans. Computers, vol. C-36, pp. 47–63 (1987).

    Article  Google Scholar 

  33. K. H. Huang and J. A. Abraham, Algorithm-based fault-tolerance for matrix operations, IEEE Trans. Computers, vol. C-33, pp. 518–529 (1984).

    Article  Google Scholar 

  34. P. Banerjee and J. A. Abraham, Bounds on algorithm-based fault tolerance in multiple processor systems, IEEE Trans. Computers, vol. C-35, pp. 296–306 (1986).

    Article  Google Scholar 

  35. J. A. Abraham, P. Banerjee, C.-Y. Chen, W. K. Fuchs, S.-Y. Kuo and A. L. N. Reddy, Fault tolerance techniques for systolic arrays, IEEE Trans. Computers, vol. C-36, pp. 65–75 (1987).

    Google Scholar 

  36. J.J. LeBlanc, LOCST: A built-in self-test technique, IEEE Design and Test, pp. 45–52 (Nov 1984).

    Google Scholar 

  37. M. A. Gruetzner, A hierarchical test approach for WSI using boundary scan logic, in Wafer Scaie Integration, G. Saucier and J. Trihle (Eds), Elsevier Science Pubs., pp. 169–175 (1986).

    Google Scholar 

  38. E. B. Eichelberger and T. W. Williams, A logic design structure for LSI testability, Proc. IEEE Design Automation Conf., pp. 462–468 (1977).

    Google Scholar 

  39. E. B. Eichelberger and E. Lindbloom, Random-pattern coverage enhancement and diagnosis for LSSD logic self-test, IBM J. Res. Dev., vol. 27, pp. 265–272 (1983).

    Article  Google Scholar 

  40. P. H. Bardell and W. H. McAnney, Self-testing of multi-chip logic modules, Proc. IEEE Int. Test Conf., pp. 200–204 (1982).

    Google Scholar 

  41. D. Komonytsky, LSI self-test using level sensitive scan design and signature analysis, Proc. IEEE Int. Test Conf., pp. 414–424 (1982).

    Google Scholar 

  42. P. H. Bardell and W. H. McAnney, Pseudorandom arrays for built-in tests, IEEE Trans. Computers, vol. C-35, pp. 653–658 (1986).

    Article  Google Scholar 

  43. S. W. Golumb, Shift Register Sequences, Aegean Press, Laguna Hills, CA (1982).

    Google Scholar 

  44. W. W. Peterson and E. J. Weldon, Error Correcting Codes, 2nd edition, The Colonial Press (1972).

    MATH  Google Scholar 

  45. J. Savir, Syndrome testable design of combinational circuits, IEEE Trans. Computers, vol. C-29, pp. 442–451 (1980). See also vol. C-29, pp. 1012–1013 (1980).

    Article  MathSciNet  Google Scholar 

  46. J. P. Robinson and N. R. Saxena, A unified view of test compression methods, IEEE Trans. Computers, vol. C-36, pp. 94–99 (1987).

    Article  Google Scholar 

  47. J. P. Hayes, Transition count testing of combinational logic circuits, IEEE Trans. Computers, vol. C-25, pp. 613–620 (1976).

    Article  MathSciNet  Google Scholar 

  48. S. M. Reddy, A note on testing logic circuits by transition counting, IEEE Trans. Computers, vol. C-26, pp. 313–314 (1977).

    Article  Google Scholar 

  49. J. P. Hayes, Generation of optimal transition count tests, IEEE Trans. Computers, vol. C-27, pp. 36–41 (1978).

    Article  MathSciNet  Google Scholar 

  50. H. Fujiwara and K. Kinoshita, Testing logic circuits with compressed data, Proc. IEEE Int. Symp. Fault-Tolerant Computing, pp. 108–113 (1978).

    Google Scholar 

  51. A. K. Susskind, Testing by verifying Walsh coefficients, IEEE Trans. Computers, vol. C-32, pp. 198–201 (1983).

    Article  Google Scholar 

  52. T.-C. Hsiao and S. C Seth, An analysis of the use of the Rademacher-Walsh spectrum in compact testing, IEEE Trans. Computers, vol. C-33, pp. 934–937 (1984).

    Article  Google Scholar 

  53. D. M. Miller and J. C. Muzio, Spectral fault signatures for single stuck-at faults in combinational circuits, IEEE Trans. Computers, vol. C-33, pp. 765–769 (1984).

    Article  Google Scholar 

  54. D. M. Miller and J. C. Muzio, Spectral fault signature for internally unate combinational networks, IEEE Trans. Computers, vol. C-32, pp. 1058–1062 (1983).

    Article  Google Scholar 

  55. S. L. Hurst, D. M. Miller and J. C. Muzio, Spectral Techniques in Digital Logic, Academic Press, NY, New York (1985).

    Google Scholar 

  56. Y. Zorian and V. K. Agarwal, Higher certainty of error coverage by output data modification, Proc. IEEE Int. Test Conf., pp. 140–147 (1984).

    Google Scholar 

  57. N. R. Saxena and J. P. Robinson, Accumulator compression testing, IEEE Trans. Computers, vol. C-33, pp. 317–321 (1986).

    Article  Google Scholar 

  58. A. Y. Chan, Easy-to-use signature analyzer accurately troubleshoots complex logic circuits, Hewlett Packard Journal, pp. 9–14 (May 1977).

    Google Scholar 

  59. R. A. Frohwerk, Signature analysis: a new digital field service method, Hewlett Packard J., pp 2–8 (May 1977).

    Google Scholar 

  60. S. Z. Hassan, Signature testing of sequential machines, IEEE Trans. Computers, vol. C-33, pp. 762–764 (1984).

    Article  Google Scholar 

  61. J. E. Smith, Measure of the effectiveness of fault signature analysis, IEEE Trans. Computers, vol. C-29, pp. 510–514 (1980).

    Article  Google Scholar 

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Authors and Affiliations

  1. AT&T Bell Laboratories, USA

    Stuart K. Tewksbury

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  1. Stuart K. Tewksbury
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© 1989 Kluwer Academic Publishers

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Tewksbury, S.K. (1989). General Testing Techniques. In: Wafer-Level Integrated Systems. The Kluwer International Series in Engineering and Computer Science, vol 70. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1625-1_7

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  • DOI: https://doi.org/10.1007/978-1-4613-1625-1_7

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8898-5

  • Online ISBN: 978-1-4613-1625-1

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