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Fault Modeling

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Wafer-Level Integrated Systems

Part of the book series: The Kluwer International Series in Engineering and Computer Science ((SECS,volume 70))

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Abstract

The objective of fault modeling is to evaluate the various errors which can occur in digital circuits as a result of the various physical faults in fabricated devices and interconnections [l]–[7]. Conceptually, this involves the three principal steps illustrated in Figure 6.1.

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Authors and Affiliations

  1. AT&T Bell Laboratories, USA

    Stuart K. Tewksbury

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© 1989 Kluwer Academic Publishers

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Tewksbury, S.K. (1989). Fault Modeling. In: Wafer-Level Integrated Systems. The Kluwer International Series in Engineering and Computer Science, vol 70. Springer, Boston, MA. https://doi.org/10.1007/978-1-4613-1625-1_6

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  • DOI: https://doi.org/10.1007/978-1-4613-1625-1_6

  • Publisher Name: Springer, Boston, MA

  • Print ISBN: 978-1-4612-8898-5

  • Online ISBN: 978-1-4613-1625-1

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