Summary

Abstract

This thesis describes the issues related to ΣΔ analog-to-digital converter (ADC) design in a systematic manner, from the top level of abstraction represented by the filters defining signal and noise transfer functions (STF, NTF), passing through the architecture-level where topology-related performance is calculated and simulated, and finally down to parameters of circuit elements like resistors and capacitors in the integrators and amplifier transconductances. The systematic approach allows the evaluation of different loop filters (order, aggressiveness, discrete-time or continuous-time implementation) with quantizers varying in resolution. Topologies explored can be single loops with only distributed feed- forwards up to multiple cascaded loops with complex structures including more feedbacks and feedforwards. For differential circuits, with switched-capacitor integrators for discrete-time (DT) loop filters and active-RC for continuous-time (CT) ones, the passive integrator components can be calculated and the power consumption can be estimated, based on top-level requirements like harmonic distortion and noise budget.