Abstract
A ΣΔ ADC requires a set of two transfer functions to be implemented. In the widely-used case of the low-pass ADCs, the two functions are a high-pass noise transfer function (NTF) and a low-pass signal transfer function (STF). They are implemented with an architecture containing a loop filter and a coarse quantizer (with lower resolution than the Nyquist-rate target) which limits the applicability of the analytical (linear) model for the noise-shaping ADC [3]. These limits of linear model can only be overcome by time-domain simulations of the fully-designed architecture. Architecture-level issues of ΣΔ ADC design are covered in this Chapter, from effects of NTF and STF design choices to effects of circuit-related non-idealities like clock jitter, which are easy to model accurately at this abstraction level [4]. Section 2.1 describes the linear model, principles and operation of a ΣΔ ADC. In Section 2.2, the design of both singleloop and cascaded, discrete-time (DT) ΣΔ ADCs is covered. A similar analysis is carried out for the continuous-time (CT) ΣΔ ADCs in Section 2.3.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
Author information
Authors and Affiliations
Rights and permissions
Copyright information
© 2004 Springer Science+Business Media New York
About this chapter
Cite this chapter
Bajdechi, O., Huijsing, J.H. (2004). Architecture-Level Analysis of Sigma-Delta ADCs. In: Systematic Design of Sigma-Delta Analog-to-Digital Converters. The Springer International Series in Engineering and Computer Science, vol 768. Springer, Boston, MA. https://doi.org/10.1007/978-1-4020-7946-7_2
Download citation
DOI: https://doi.org/10.1007/978-1-4020-7946-7_2
Publisher Name: Springer, Boston, MA
Print ISBN: 978-1-4419-5456-5
Online ISBN: 978-1-4020-7946-7
eBook Packages: Springer Book Archive