Abstract
Many DSP functions can be implemented as arrays of simple Processing Elements (PEs) connected to their nearest neighbours in a regular manner. Field Programmable Gate Arrays consist of an array of user-configurable logic blocks and a matrix of user configurable interconnection between the logic blocks. Thus FPGAs are prime candidates for implementing regular arrays. In this paper we present FPGA Regular Array Description Language (FRADL) which will map the regular array into a FPGA.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
S. Bellis, W. Marnane, and P. Fish. Systolic Architectures for the Modified Covarience Spectral Estimator used with Ultrasonic Doppler Blood Flow Detectors. In Proceedings of IRISH DSP and Control Colloquium, pages 71–78, 1994.
M.B. Gokhale, S. Kopser, S.P. Lucas, and R.G. Minnich. The Logic Description Generator. In S. Y. Kung, E. Swartzlander, J. Fortes, and K. W. Przytula, editors, Application Specific Array Processors, pages 111–120. IEEE Computer Society Press, September 1990.
Kai Hwang. Computer Arithmetic, Principles, Architecture and Design. John Wiley & Sons, 1979.
C. Jordan and W. Marnane. Prototyping Systolic Arrays using Field Programmable Gate Arrays. In Proceedings of IRISH DSP and Control Colloquium, pages 79–86, 1994.
W. P. Marnane, C. J. Jordan, and F. J. O' Reilly. Synthesising a FIR Filter onto a FPGA. In Proceedings of IRISH DSP and Control Colloquium, June 1995.
J. V. McCanny, J. G. McWhirter, and E. Swartzlander, editors. Systolic Array Processors. Prentice Hall, 1989.
J. V. McCanny, K. W. Wood, J. G. McWhirter, and C. J. Oliver. The Relationship Between Word and Bit Level Systolic Arrays as Applied to Matrix × Matrix Multiplication. Proceedings of SPIE Int. Soc. Opt. Eng., 495:114–120, 1984.
W. R. Moore, A. P. H. McCabe, and R. B. Urquhurt, editors. Systolic Arrays. Adam Hilger, 1987.
R. B. Urquhart and D. Wood. Systolic matrix and vector multiplication methods for signal processing. IEE Proceedings Part F, 131(6):623–631, October 1984.
M. Valero, S. Y. Kung, T. Lang, and J. Fortes, editors. Application Specific Array Processors. IEEE Computer Society Press, September 1991.
H. Le Verge, C. Mauras, and P Quinton. The ALPHA Language and its use for the Design of Systolic Arrays. Journal of VLSI Signal Processing, (3):173–182, 1991.
D. K. Wilde and O. Sié. Regular array synthesis using alpha. In Proc. International Conference on Application-Specific Array Processors — ASAP'94, pages 200–211, 1994.
Xlinx Inc., San Jose, California, USA. The Programmable Gate Array Data Book, 1991.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1995 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Marnane, W.P., Jordan, C.N., O'Reilly, F.J. (1995). Compiling regular arrays onto FPGAs. In: Moore, W., Luk, W. (eds) Field-Programmable Logic and Applications. FPL 1995. Lecture Notes in Computer Science, vol 975. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-60294-1_111
Download citation
DOI: https://doi.org/10.1007/3-540-60294-1_111
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-60294-1
Online ISBN: 978-3-540-44786-3
eBook Packages: Springer Book Archive