Abstract
This paper presents an efficient technique for realizing Data Path using FPGAs. The approach is based on exploiting the iterative structure of the datapath modules and identifying ’largest’ slices of connected modules that can be mapped onto each CLB. The mapping process employs a fast decomposition algorithm for checking whether a set of slices can be realized by a single CLB. Comparison with manufacturer's proprietary software for a set of High-level synthesis benchmark structures show a significant reduction in CLB count. Another advantage of our technique is that CLB boundaries in the final design are aligned to RTL module boundaries providing modularity and ease in testing. Thus this technique is very suitable for integration as a technology mapping phase with a high-level synthesis package.
This is a preview of subscription content, log in via an institution to check access.
Preview
Unable to display preview. Download preview PDF.
Similar content being viewed by others
References
R. Murgai, et al., ”Logic Synthesis for Programmable Gate Arrays”, Proc. 27th Design Automation Conf., June 1990, pp. 620–625.
Xilinx Programmable Gate Array Users' Guide, 1988 Xilinx, Inc.
R. J. Francis, J. Rose, K. Chung, ”Chortle: A Technology Mapping Program for Lookup Table based Field Programmable Gate Arrays”, Proc. 27th Design Automation Conf., June 1990, pp. 613–619.
R. J. Francis, J. Rose, Z. Vranesic, ” Chortle-crf: Fast Technology Mapping for Look-up Table-Based FPGAs”, Proc. 28th Design Automation Conf. 1991, pp.227–233.
D. Filo, J. C. Yang, F. Malihot, G.D. Micheli, ”Technology Mapping for a Two-output RAM-based Field Programmable Gate Arrays”, European Design Automation Conf., February 1991, pp. 534–538.
K. Karplus, ”Xmap: A Technology Mapper for Table-Lookup Field Programmable Gate Arrays”, Proc. 28th Design Automation Conf., June 1991, pp. 240–243.
Nam-Sung Woo, ”A heuristic Method for FPGA Technology Mapping Based on Edge Visibility”, Proc. 28th Design Automation Conf.,June 1991, pp. 248–251.
R. J. Francis, J. Rose, Z. Vranesic, ”Technology Mapping of Look-up Table-Based FPGAs for performance”, Proc. Int. Conf. on CAD, 1991, pp.568–571.
Kuang-Chien Chen et al., ”DAG-Map: Graph-Based FPGA Technology Mapping for Delay Optimization”, IEEE Design & Test, September 1992, pp. 7–20.
R. Murgai et al., ”Performance-Directed Synthesis for Table Look-up Programmable Gate Arrays”, Proc. Int. Conf. on CAD, 1991, pp. 572–575.
P. J. Roth and R. M. Karp, ”Minimization over Boolean graphs”, IBM Journal of Research and Development vol. 6/No.2/April 1962 pp. 227–238.
Anshul Kumar et al. ”IDEAS: A Tool for VLSI CAD ”, IEEE Design and Test, 1989, pp.50–57.
M. V. Rao, M. Balakrishnan and Anshul Kumar, ”DESSERT: Design Space Exploration of RT Level Components”, Proc. IEEE/ACM 6th Int. Conf. on VLSI Design'93, January 1993, pp. 299–303.
A. R. Naseer, M. Balakrishnan and Anshul Kumar, ”FAST: FPGA targeted RTL structure Synthesis Technique”, Proc. IEEE/ACM 7th Int. Conf. on VLSI Design'94 January 1994, pp. 21–24.
A. R. Naseer, M. Balakrishnan and Anshul Kumar, ”A technique for synthesizing Data Part using FPGAs”, Proc. IEEE/ACM 2nd Int. Workshop on Field Programmable Gate Arrays, Berkeley, February 1994.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1994 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Naseer, A.R., Balakrishnan, M., Kumar, A. (1994). An efficient technique for mapping RTL structures onto FPGAs. In: Hartenstein, R.W., Servít, M.Z. (eds) Field-Programmable Logic Architectures, Synthesis and Applications. FPL 1994. Lecture Notes in Computer Science, vol 849. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-58419-6_73
Download citation
DOI: https://doi.org/10.1007/3-540-58419-6_73
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-58419-3
Online ISBN: 978-3-540-48783-8
eBook Packages: Springer Book Archive