Abstract
Network on Chip (NoC) is a new paradigm for designing large and complex systems on chips (SoCs). In this paradigm, a packet switched network is provided for on-chip communication. The NoC paradigm provides the required scalability and reusability to reduce design time of SoCs. A NoC simulator is an important tool required to support development of designs based on a NoC architecture. In this paper, we describe the design of such a simulator using the ITU-T Specification Description Language (SDL). Features of SDL for representing structural hierarchy using blocks, concurrent processes and dynamic generation of processes, communication channels, user defined data types and timers are useful for modelling a NoC architecture at various levels of communication protocols. We use an event driven SDL simulator to carry out interesting experiments to evaluate various architectural options such as buffer size in switches, and their effect on the performance such as delay and packet loss.
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References
S. Kumar, A. Jantsch, J-P. Soininen, M. Forsell, M. Millberg, J. Öberg, K. Tiensyrjä, A. Hemani. A network on chip architecture and design methodology. Proceedings of IEEE Computer Society Annual Symposium on VLSI (April 2002)
S. Kumar. On Packet Switched Networks for On-Chip Commincation. Book chapter in a forthcoming book entitled Network on Chip (Editors Axel Jantsch and Hannu Tenhunen), Pulblishers Kluwer Publication (March 2003)
E. Rijpkema, K. Goossens, P. Wielage. A Router Architecture for Networks on Silicon. Proceedings of Rogress, 2nd Workshop on Embedded Systems (2001)
L. Benini, G. De Micheli. Networks on Chips: A New SoC Paradigm. IEEE Computer Society (2002)
P. Wielage, K. Goosens. Networks on Silicon: Blessing or Nightmare?. Euromicro Symposium On Digital System Design (DSD 2002), Dortmund, Germany (Sep. 2002)
D. Wiklund, D. Liu. SoCBUS: The solution of high communication bandwidth on chip and short TTM. Proc. of the Real-Time and Embedded Computing Conference, Gothenburg, Sweden (Sep. 2002)
Y. Sun, S. Kumar, A. Jantsch. Simulation and Evaluation for a network on chip architecture using NS-2. Proceedings 20th NORCHIP conference, Copenhagen (Nov. 2002)
R. Thid. A Time Driven Network on Chip Simulator Implemented in C++. Master of Science Thesis, Laboratory of Electronic and Computer Systems, Royal Institute of Technology (KTH), Stockholm, Sweden (2002)
G.N. Higginbottom. Performance Evaluation of Communication Networks. Artech House (1998)
A. Olsen, O. Fægemand, B. Møller-Pedersen, R. Reed, J.R.W. Smith. System Engineering Using SDL-92. North-Holland (1994)
J. Ellsberger, D. Hogrefe, A. Sarma. SDL Formal Object-oriented Language for Communicating Systems. Prentice Hall (1997)
R. Holsmark, M. Högberg. Modelling and prototyping of a Network on Chip. Master of Science Thesis, Embedded Systems, Department of Electronics and Computer Engineering, School of Engineering, Jönköping University, Sweden (2002)
“Telelogic Tau 4.3” Telelogic AB (2001)
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Holsmark, R., Högberg, M., Kumar, S. (2003). Modelling and Evaluation of a Network on Chip Architecture Using SDL. In: Reed, R., Reed, J. (eds) SDL 2003: System Design. SDL 2003. Lecture Notes in Computer Science, vol 2708. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-45075-0_10
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DOI: https://doi.org/10.1007/3-540-45075-0_10
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