Abstract
The LTL model checker that we use provides sound decomposition mechanisms within a purely model checking environment. We have exploited these mechanisms to successfully verify a wide spectrum of large and complex circuits. This paper describes a variety of the decomposition techniques that we have used as part of a large industrial formal verification effort on the Intel Pentium R 4 (Willamette) processor.
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Beers, R., Ghughal, R., Aagaard, M. (2002). Applications of Hierarchical Verification in Model Checking. In: Hunt, W.A., Johnson, S.D. (eds) Formal Methods in Computer-Aided Design. FMCAD 2000. Lecture Notes in Computer Science, vol 1954. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-40922-X_1
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DOI: https://doi.org/10.1007/3-540-40922-X_1
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