Abstract
We present a technique for synthesizing systolic arrays which have non-uniform data flow governed by control signals. The starting point for the synthesis is a Recurrence Equation with Linear Depencencies (RELD) which is a generalization of the simple recurrences encountered in mathematics. A large class of programs, including all (single and multiple) nested-loop programs can be described by such recurrences. In this paper we extend some of our earlier work [17] in two principal directions. Firstly, we describe a transformation called multistage pipelining and show that it yields recurrences that have linear conditional expressions governing the computation. Secondly, we discuss how it is possible to automatically derive control signals that govern the data flow by applying the same pipelining transformations to these linear conditional expressions. The approach is illustrated by deriving the Guibas-Kung-Thompson architecture for optimum string parenthesization.
Supported by a University of Utah Graduate Research Fellowship
Supported by an IBM faculty development grant.
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Rajopadhye, S.V., Fujimoto, R.M. (1987). Systolic array synthesis by static analysis of program dependencies. In: de Bakker, J.W., Nijman, A.J., Treleaven, P.C. (eds) PARLE Parallel Architectures and Languages Europe. PARLE 1987. Lecture Notes in Computer Science, vol 258. Springer, Berlin, Heidelberg. https://doi.org/10.1007/3-540-17943-7_135
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DOI: https://doi.org/10.1007/3-540-17943-7_135
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