Abstract
We consider some problems related in VLSI Layout Analysis and Verification and model them as problems of reporting enclosures of polygons. Algorithms are provided using techniques of computational geometry, which solve these problems in optimal time and space.
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Mathematics Subject Classification (2000): 68W99, 51-04.
*Work done while the author was a student at I.I.I.T. Hyderabad
†Supported in part by grant SR/S/EECE/22/2004 from the Department of Science and Technology, Govt. of India
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Kundeti, V.K., Gupta, P. Optimal Algorithms for Some Polygon Enclosure Problems for VLSI Layout Analysis. J Math Model Algor 5, 259–271 (2006). https://doi.org/10.1007/s10852-005-9008-z
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DOI: https://doi.org/10.1007/s10852-005-9008-z