1 INTRODUCTION

Organic semiconductors have shown great potential to replace the conventional amorphous silicon (a-Si) as the material for active matrix displays on thin-film transistors (TFTs). Organic electronic materials are superior to inorganic materials in terms of low-cost manufacturing capability. Research based on organic semiconductors has developed large-area electronic devices such as OTFT, organic light-emitting diodes (OLEDs), organic solar cells (OSC), etc. OTFTs offer a wide range of applications over the past two decades, such as low-cost displays [1], organic memories [2], key radio-frequency tags [3], polymer circuits, and sensors [4]. The performance of OTFT for real-time commercial applications depends on various parameters such as On-to-Off current ratio, mobility, current density, electric field, and the threshold voltage in the device [5]. These parameters are often affected by the combination of the various active materials, the geometry of the device, thin-film particle size, trap state, and thickness of semiconductor layers [6, 7]. To improve device performance, it is necessary to understand the behavior of semiconductor layer and semiconductor-dielectric interface because it extremely affects the charge transport in the device due to charge localization [8]. The performance of the device degrades significantly due to defects available at the interface level. Thus semiconductor layer thickness is one of the important parameters for device performance. The semiconductor layer is critical to OTFT because it can accommodate the internal transport of charge carriers, which primarily determines the performance of the device. OTFT’s can be synthesized with a variety of functional groups and variable thickness of OSC for desired electrical properties. Many researcher’s studies [9, 10] have also reported the effect of active layer thickness on parasitic access resistance. This would be resulting in changes in source and drain resistance, which affects the device performance. Various studies [11–16] have been reported for the impact of semiconductor layer thickness on the effectiveness of OTFT with a variety of organic semiconductors as P3HT [6], 4QT4 (Dibutylquaterthiophene) [9]. Most research efforts have been dedicated to describe the morphology of the active layer, interface at dielectric.

This paper covers the detailed study of electrical parameter and microscopic analysis of physics-based parameters with variation in thickness of the semiconductor layer from a deep device physics point of view. The thickness of the active layer is varied to find their effect on physical parameters such as charge density, electric field, On-to-Off current ratio, and mobility.

Due to the experimental limitations in providing evidence, there is still a lack of detailed understanding from a deep physics point of view. By doing analysis based on experimental data only, it is very difficult to know about real physics involved with the device. Two-dimensional physical numerical modeling proved to be very useful in understanding the microscopic behavior of the device. Using 2D simulation, it is also easy to study those various physical quantities which is difficult to understand with experimental data alone. Hence, the detailed analysis of physical quantities and the electrical parameters is done using two-dimensional numerical simulations. The two-dimensional device simulation would be helpful to become familiar with the basic functions of the device as well as the optimization of the device structure.

2 DEVICE SIMULATION

This section introduces the device structure under consideration and simulation parameter used for our designed OTFT and device physics involved in it.

2.1 Experimentally Verified Numerical Simulation for BGTC OTFT

A schematic diagram of TIPS-pentacene based OTFT is presented in Fig. 1.

Fig. 1.
figure 1

BGTC structure of OTFT showing x, y distance along with the thickness of semiconductor layer.

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Two-dimensional numerical simulation is performed using a device simulator named ATLAS (SILVACO), in which the finite element method is used. Simulator solves drift-diffusion equations, continuity equations, and Poisson’s equation for electrons and holes. Bottom gate top contact (BGTC) TIPS-pentacene based OTFTs as shown in Fig. 1 is simulated for validation. All structural parameters of the simulated device are given in Table 1.

Table 1. Device dimensions for numerical simulation
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The material properties of TIPS-pentacene semiconductors are listed in Table 2.

Table 2. Parameters of material for ATLAS simulation of the OTFT [15]
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As defined in Table 2, the relative permittivity, hole affinity, and energy bandgap of TIPS-pentacene are considered as 4, 2.8, and 1.8 eV, respectively [15].

The density of states in the valence band and conduction band is taken as 2.0 × 1021 cm–3 [15]. After enabling calibration of the simulator, the same device with scaling down thickness Tosc of organic semiconducting material from 500 to 100 nm is simulated keeping all other parameters constant.

The schematic of the structure under consideration is similar to one studied experimentally by Deepak Bharti et al. [16]. For validation of simulated device characteristic, experimental data are taken from [16], where device was fabricated using drop-cast technique. In the device, the silicon oxide layer of 300 nm placed on silicon substrate worked as a gate dielectric. Next, an organic semiconductor layer of TIPS-pentacene having a thickness of 500 nm was placed on the gate dielectric. Gold contacts with a thickness of 200 nm were deposited on the top to define source/drain electrodes. The OTFT has a channel length of 237 μm and a channel width of 178 μm.

2.2 Device Physics Involved in OTFT

To explain the charge transport process in organic material like TIPS-pentacene, the Poole–Frenkel mobility model is used in ATLAS simulation. In the Poole–Frenkel model, the conduction of charge carriers occurs due to improved excitation of trapped carriers in the electric field. Poole–Frenkel mobility model [18] in mathematical form can be presented as in Eq. (1).

$$\mu (E) = {{\mu }_{0}}\exp \left[ { - \frac{{\Delta {{E}_{a}}}}{{kT}} + \left( {\frac{\beta }{{kT}} - \gamma } \right)} \right]\sqrt E ,$$
(1)

μ(E) is field-dependent mobility, zero-field mobility is given by μ0, ΔEa is zero field activation, β is the Poole–Frenkel factor, γ is the fitting parameter, the electric field is denoted by E, Boltzmann constant is k and T denotes temperature. Thermionic emission and Poole–Frankel barrier lowering are included in the ATLAS simulations.

The physics involved in given ATLAS simulation can be calculated by solving basic device equations simultaneously including Poisson’s equation [21], electron and hole continuity equation, charge transfer equation, and defect density of states equation. The Poisson equation [22, 23] determines the electric field intensity in the given device based on the internal movement of the carriers and the distribution of the fixed charges.

$$G(E) = {{G}_{{{\text{GA}}}}} + {{G}_{{{\text{GD}}}}} + {{G}_{{{\text{TA}}}}} + {{G}_{{{\text{TD}}}}},$$
(2)

where

$${{G}_{{{\text{TA}}}}}(E) = {{n}_{{{\text{TA}}}}}\exp \left[ {\frac{{E - {{E}_{C}}}}{{{{w}_{{{\text{TA}}}}}}}} \right],$$
(3)
$${{G}_{{{\text{TD}}}}}(E) = {{n}_{{{\text{TD}}}}}\exp \left[ {\frac{{E - {{E}_{V}}}}{{{{w}_{{{\text{TD}}}}}}}} \right],$$
(4)
$${{G}_{{{\text{GA}}}}}(E) = {{n}_{{{\text{GA}}}}}\exp \left[ { - {{{\left[ {\frac{{{{E}_{{{\text{GA}}}}} - E}}{{{{w}_{{{\text{GA}}}}}}}} \right]}}^{2}}} \right],$$
(5)
$${{G}_{{{\text{GD}}}}} = {{n}_{{{\text{GD}}}}}\exp \left[ { - {{{\left[ {\frac{{E - {{E}_{{{\text{GD}}}}}}}{{{{w}_{{{\text{GD}}}}}}}} \right]}}^{2}}} \right].$$
(6)

For studying the physics of density of states of organic semiconductor layers, Gaussian density of states model is used in simulations. Using the Gaussian distribution density of states G(E) containing four bands (tail bands and deep energy level bands) can be modeled [18] as given in Eqs. (2)–(6). Conduction band energy (EC), valence energy band (EV), and trap energy (E) are labelled with subscripts A, T, G, D representing the acceptor, tail, Gaussian, and donor states, respectively. nTD, nTA, wTD, wTA are conduction band edge intercept density, valance band edge intercept density, conduction band characteristic attenuation energy, and valance band characteristic attenuation energy, respectively, for exponential tails. nGA, nGD, wGD, wGA are acceptor state density, donor state density, acceptor characteristic attenuation energy, and donor characteristic attenuation energy for Gaussian distribution. EGA and EGD are peak energy for Gaussian distribution.

3 RESULTS AND DISCUSSION

In this section, the device characteristic of organic thin-film transistors (OTFTs) fabricated with TIPS-pentacene is validated with the simulated result using the finite element method for 2D numerical simulations. The device simulation includes a field-dependent mobility model including traps. Later the performance of OTFT in terms of On-to-Off ratio, electric field, and current density is examined for different active layer thickness varying from 500 to 100 nm.

The device as given in Fig. 2 is provided with a forward sweep with the step of –5 V with an incremental gate bias voltage from 0 to –25 V.

Fig. 2.
figure 2

Output characteristics of TIPS-pentacene TFTs: experimental vs numerical simulation results.

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Simulated output characteristics of a TIPS-pentacene OTFT using device parameters in Table 2 are validated with experimental characteristics and almost a close matching is observed as shown in Fig. 2. Output characteristics are exhibiting the saturation nature at higher drain voltage.

Figure 3 transfer characteristic (drain current versus gate voltage) for different thicknesses of semiconductors such as 500, 300, 200, and 100 nm was simulated with the same W/L and drain voltage VDS of –30 V. It can be observed that Off current is strongly dependent on the thickness of the semiconductor layer. Off current raises with an increase in semiconductor thickness due to an increase in the bulk current but on current almost remains constant.

Fig. 3.
figure 3

Simulated transfer characteristics for devices with an active layer thickness Tosc of 500, 300, 200, and 100 nm and VGS of –30 V.

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Figure 4 shows that the majority of the current in the device flows from the accumulation area that is near the interface of the dielectric and OSC layer. Bulk current is also associated with drain current which increases with an increase in the thickness of the TIPS-pentacene but the share of the bulk current in total drain current is much less.

Fig. 4.
figure 4

Current flow lines in the active layer.

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The larger thickness of the active layer leads to more of the current in the OTFT due to the presence of more bulk charge. In the device, injection of current starts from source contact then passes through the semiconductor film, reaches the dielectric interface, and finally takes out from the drain contact. As shown in Fig. 5, at 100, 200, 300, and 500 nm vertical electric field magnitude have almost the same magnitude but higher electric field is generated in the thinner active layer, which forces more charge carrier to the semiconductor dielectric interface thus the charge localization increase near the surface of dielectric field.

Fig. 5.
figure 5

Vertical electric field profile along x-distance in structure.

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Charge accumulation is slightly away from the surface of dielectric so that accumulated charge carriers go across less trapping due to dipoles near the surface of the insulator. This shows improved device performance for the thinner active layer. It is clear from Fig. 6 that the device with a thinner active layer has more current density due to the lesser area.

Fig. 6.
figure 6

Hole current density along x-distance at 5 nm above the OSC-dielectric interface.

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The majority of the current in the device flows from the accumulation area that is near the interface of the dielectric and OSC layer. Table 3 shows the comparison of electrical and physical parameters like electric field, current density mobility, maximum drain current, and On-to-Off current ratio at a different thicknesses of semiconductor layer keeping all other parameters constant.

Table 3. Comparison of electrical characteristics for various semiconductor thickness
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The device with a thinner active layer shows better performance. Thinner active layer leads to less Off current and hence increase in On-to-Off current ratio due to almost constant On current.

4 CONCLUSIONS

In conclusion, the impact of the scaling down the semiconductor thickness (varying from 500 to 100 nm) on parameters such as electric field, current density, On-to-Off current ratio, and mobility is comparatively analyzed with the help of a field-dependent mobility model and density of defects states model in ATLAS simulation. Also the experimental and simulated characteristics of the device are reasonably matched. It has been observed that the device with a thinner active layer performs better and improves overall performance. Optimization of thickness is one of the important parameters to improve device performance and employability in real-time applications such as displays, RFID tags and practical switching applications.