Introduction

With the expansion of generative AI, which is computationally intensive, the hardware used for servers must have higher processing speeds. This raises the problem of large hardware power consumption and the need for power-saving measures1. Thus, hardware in the AI era should satisfy both the requirements concurrently: high processing speed and low power consumption2. To satisfy these requirements or solve a disadvantage of Neumann computing, a technique for shortening the distance between a memory device and an arithmetic unit such as Central Processing Unit (CPU) or Graphics Processing Unit (GPU) is required. In this regard, three-dimensional (3D) stacking using oxide semiconductors is a candidate technique3.

Oxide semiconductors, which can be formed at low temperatures, have been extensively reported as channel materials for displays and very-large-scale integration (VLSI) circuits4,5,6,7,8,9,10,11,12,13,14,15,16,17,18,19,20,21,22,23,24,25,26,27,28,29,30,31,32,33,34,35. In particular, c-axis-aligned crystalline indium gallium zinc oxide (CAAC-IGZO) has proven to be practical in driving transistors of displays for smartphones and augmented reality/virtual reality11. CAAC-IGZO is IGZO having c-axis alignment perpendicular to a formation surface and having no clear grain boundaries4,36,37. We have shown that the off-state current of CAAC-IGZO field-effect transistors (FETs) can be as small as 10−21A μm−1 at room temperature, indicating the potential of oxide semiconductors to meet the recent demand for power saving5,38,39. However, CAAC-IGZO still suffers from lower on-state current (Ion) relative to that of bulk Si and a disadvantage in application to LSI requiring high-speed processing.

Conversely, the Ion of amorphous or polycrystalline In2O3, an oxide semiconductor type, is comparable to that of low-temperature polysilicon-based transistors and is expected to become higher40,41,42,43,44,45,46,47,48. In2O3 is crystallized at low temperature, and the use of In2O3 in thin film transistors has been reported since 200745. In 2011, we proposed the applications of In2O3 to vertical transistors and LSI circuits10. Although polycrystalline In2O3 is expected to have higher Ion, polycrystalline In2O3 has grain boundaries that impede the reduction in characteristic variation compared with CAAC-IGZO. In this paper, we formed a prototype of a high-integration vertical transistor suitable for 3D VLSI using single-crystalline In2O3 in its channel region to reduce the variation in In2O3 characteristics. For the off-state current that is a key to lower power consumption, we examined whether the off-state current of single-crystalline In2O3 is as low as that of CAAC-IGZO. To meet the need for 3D stacking, both high processing speed and low power consumption can be achieved concurrently when characteristics variations and off-state current can be reduced by forming single-crystalline In2O3 on an insulating film.

Results

Challenges for forming single-crystalline In2O3

For single crystallization of In2O3, this involves reducing film impurities and reducing crystal nucleus density. To reduce impurities in films during the atomic layer deposition (ALD) of In2O349,50,51,52,53,54, particularly, the In precursor should be highly purified to a 6 N to 7 N level. To reduce the crystal nucleus density, eliminating crystal nuclei other than those used as In2O3 growth seeds is crucial. Additionally, selecting a seed suitable for bixbyite-type In2O3 growth is important.

Seed for crystallization

We consider that the use of a seed, which is the starting point of crystallization, with an appropriate orientation can facilitate single crystallization of In2O3. Epitaxial growth is possible55,56 owing to a small lattice mismatch between yttria-stabilized zirconia (YSZ) and In2O355. Figure 1a shows a STEM image of In2O3 formed by ALD on a single-crystalline YSZ (Cubic) (111) substrate, which has the same crystal structure as In2O3. As shown in Fig. 1a, we also successfully achieved single crystallization of In2O3 using a surface of the YSZ (111) substrate as a seed. However, since the method using the YSZ (111) substrate is not suitable for 3D stacking of VLSI, it is necessary to develop a method for forming single-crystalline In2O3 in the desired locations on an insulating film.

Fig. 1: Cross-sectional images of samples where In2O3 is formed.
figure 1

a Cross-sectional HAADF-STEM image of a sample where In2O3 is formed on a YSZ (111) substrate by ALD. b Cross-sectional TEM image with length measurements of a sample where In2O3 is formed on CAAC-IGZO by ALD. Both the CAAC-IGZO and In2O3 films were baked for 1 h at 400 °C in N2 atmosphere. A cube on the right side shows the crystal orientation.

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In view of this, we examined the use of CAAC-IGZO instead of YSZ. Figure 1b shows a cross-sectional transmission electron microscopy (TEM) image of an In2O3 film formed on a CAAC-IGZO film by ALD, in which single-crystalline In2O3 {222} formed on the (001) plane of CAAC-IGZO can be observed. The interplanar spacing d222 of the In2O3 atomic layers stacked in the direction perpendicular to the (001) plane of CAAC-IGZO is 2.94 Å. The lattice spacing of IGZO in the vertical direction of Fig. 1b is 2.88 Å, which is almost equal to the interplanar spacing d222 of the In2O3 atomic layers. The lattice spacing of IGZO in the horizontal direction is 1.65 Å and the interplanar spacing d440 of the In2O3 atomic layers is 1.76 Å—a difference of approximately 6%.

Then, why the single crystallization on the CAAC-IGZO film can be achieved is described. Figure 2a shows the calculation results of the interface models by geometrical calculation57,58,59. Figure 2a compares the lattice mismatches and the bonding cross-sectional areas of super-cells where an In2O3 (Cubic, Ia\(\bar{3}\)) film is placed on the YSZ (111) substrate and the (001) plane of InGaZnO4 serving as the seeds. The lattice mismatch can be represented using Formula (1):

$$\Delta =\left(\frac{{L}_{f}}{{L}_{b}}-1\right)\times 100$$
(1)

where \(\Delta\) represents the lattice mismatch (%), Lf represents the thin-film (In2O3) lattice constant, and Lb represents the base layer (YSZ or IGZO) lattice constant. In the case where the lattice mismatch differs depending on the crystal axis, lattice mismatch is shown for each case.

Fig. 2: Calculation results of In2O3 interface models by geometrical calculation.
figure 2

a Calculation of lattice mismatch between In2O3 and base layers, which are single-crystalline YSZ and InGaZnO4 serving as seeds for single crystallization of In2O3. To determine an interface with a high lattice match between different kinds of materials, super-cells having two planes (e.g., a combination of an In2O3 (001) plane and an IGZO (001) plane) forming the interface were newly set. The mismatch degree of lattice constants (a’, b’) and a bonding cross-sectional area at the interface of the super-cells are shown, respectively, as “Lattice mismatch” and “Cross-sectional area.” It is indicated that as the lattice mismatch and the bonding cross-sectional area decrease, the lattice match at the interface between the different kinds of materials increases. b Comparison of the energy of interfaces between amorphous In2O3 and each plane of single crystalline In2O3.

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When the (001) or (111) plane of In2O3 is assumed to be formed on the (001) plane of IGZO (in this paper, IGZO belonging to a trigonal system is represented by a hexagonal lattice and denoted by (hkl) for describing lattice match with a cubic lattice), the lattice mismatch is 0.55%, which is lower than that with the YSZ (111) substrate, and the cross-sectional area is 179.3 Å2, which is very close to 184.3 Å2 of an assumed cross-sectional area between the (111) plane of In2O3 and the YSZ (111) substrate.

Figure 2b compares the energy of interfaces between amorphous In2O3 and each plane of single-crystalline In2O3 calculated by molecular dynamics calculation. The lowest interface energy is 1.92 (eV nm−2) at the (111) plane, which indicates that single crystallization of In2O3 is progressed such that the (111) plane surface area becomes the largest.

Figure 3 shows the atomic arrangement of IGZO and In2O3. Figure 3a shows the atomic arrangement of the single-crystalline IGZO seen in the direction perpendicular to the c-axis. IGZO has a natural cleavage plane between the GaZnO planes. Figure 3b shows the atomic arrangement of the single-crystalline IGZO seen in the c-axis direction, in which the nearest metal–metal distance is 3.30 Å. Figure 3c shows the atomic arrangement of the (111) plane of In2O3 seen from [111], in which the In–In distances are 3.34 to 3.36 Å. These distances are almost equal to the In–In distance of 3.30 Å in the single-crystalline IGZO. Furthermore, both single-crystalline IGZO and the (111) plane of In2O3 have three rotation axes and hexagonal atomic arrangements. As shown in Fig. 2a, the lattice mismatch and cross-sectional area between the (001) plane of In2O3 and the single-crystalline IGZO are large. This proves that the (001) plane of CAAC-IGZO has an atomic arrangement that can serve as a seed for the crystallization of the (111) plane of In2O3. Thus, as shown in Fig. 1b, the (111) plane of In2O3 (111) is crystallized on the (001) plane of CAAC-IGZO. This indicates that when In2O3 is crystallized using CAAC-IGZO as a seed, the crystal orientation of In2O3 can be controlled.

Fig. 3: Atomic arrangement in crystal planes of single-crystalline IGZO and single-crystalline In2O3.
figure 3

a Crystalline IGZO seen from the direction perpendicular to the c-axis. b Layers of the (001) plane of IGZO seen from the c-axis direction. c The (111) plane of the single-crystalline In2O3.

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Vertical-channel FET with single-crystalline In2O3 channel

To estimate the electrical characteristics of an FET with a single-crystalline In2O3 channel, a prototype vertical-channel FET (VFET) with an In2O3 channel having no grain boundaries in a channel region was fabricated (Fig. 4a)60,61,62,63,64,65,66. The FET is circular when seen from the above, and the diameter of a cylindrical portion and the interlayer insulator thickness are 60 nmɸ and 95 nm, respectively. In the vertical-channel FET, In2O3 between the upper source and drain (S/D) electrodes and the lower S/D electrodes in the vertical direction serves as a channel region. The vertical-channel FET was fabricated through the following process (Fig. 4b). Lower S/D electrodes, an interlayer insulator film, and upper S/D electrodes were successively formed, and then a channel hole was formed. Next, a 2-nm-thick CAAC-IGZO film serving as a seed layer was formed over the upper S/D electrodes by physical vapor deposition (PVD). A stack of tungsten and silicon-doped indium tin oxide thereover was used for each of the upper and lower S/D electrodes. Then, a 10-nm-thick In2O3 film was formed by ALD over and in the cylindrical portion. The In2O3 film was formed at 200 °C using an In(C2H5)3 precursor and an O3 oxidizer. Different conditions of the oxidation time were set in advance, and the In2O3 film was formed with an oxidation time of 9 s, which is a condition under which In2O3 with a large grain size was obtained. Next, a gate insulator and gate electrodes were formed.

Fig. 4: Details of VFET fabricated to estimate electrical characteristics.
figure 4

a Schematic cross-sectional structure and (b) manufacturing process of VFET. A CAAC-IGZO film (seed) is formed over the upper S/D electrodes.

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Figure 5 is a cross-sectional TEM image of the prototype VFET using single-crystalline In2O3 in its channel portion. According to the STEM-EDX line analysis, Ga and Zn derived from the IGZO were detected over the upper S/D electrodes, whereas they were hardly detected over the lower S/D electrodes (Figs. 6a to 6d). This is probably because the CAAC-IGZO seed layer, which was formed by PVD, was not formed in the deep and fine channel hole37. This indicates that IGZO might be slightly formed over the lower S/D electrodes but is too thin to be recognized as a film and thus does not function as the CAAC-IGZO seed layer. Figure 6e–g shows the results of Fast Fourier transform (FFT) analysis on the channel region between the upper S/D electrodes and the lower S/D electrodes. As shown in Fig. 5, the crystal orientation of the In2O3 on the top surface of the (001) plane of the IGZO was [111] in an almost perpendicular direction with respect to the substrate. In addition, in the channel region, the uniform FFT pattern was obtained continuously, and the crystal orientation of In2O3 was [111] in the almost perpendicular direction, and was \([\bar{11}2]\) in the almost horizontal direction with respect to the substrate. Furthermore, on the side surface of the upper S/D electrode, the crystal orientation of the crystalline In2O3 was [111] in the perpendicular direction and was \([\bar{11}2]\) toward the electrode. In other words, the In2O3 crystal has a uniform orientation along the side surface of the insulating film and is smoothly curved, even in the edge region. This demonstrates that as long as the (001) plane of the CAAC-IGZO seed is flat and smooth, the In2O3 is single-crystallized in a direction under the influence of the seed without generating grain boundaries even at positions far from the seed or on curved or vertical surfaces with planes that are not necessarily parallel to that of the seed. This single crystallization has reproducibility, and was also observed in a device of another lot.

Fig. 5: Cross-sectional TEM image of VFET with single-crystalline In2O3 channel formed with CAAC-IGZO seed.
figure 5

a Image of the VFET and its surrounding area. b Image of the entire VFET in a green square region denoted by 1 in (a). c, d Enlarged views of a red square region denoted by 2 and a blue squre region denoted by 3 in (b). The channel-hole diameter is 60 nmɸ. The VFETs are arranged at a density of 4.8 μm−2 with an x pitch of 380 nm and a y pitch of 540 nm, which is the density applicable to LSI devices. The seed is a 2-nm-thick CAAC-IGZO film, and a 10-nm-thick In2O3 film formed under the condition where the oxidation time during which O3 flows was 9 s is used for a channel region. The yellow dashed line in (c) indicates a grain boundary, which was not observed in the channel region between the upper S/D electrodes and the lower S/D electrodes. In the channel region, the semiconductor layer that has a crystal orientation in one direction and does not have grain boundaries is a single crystalline layer.

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Fig. 6: Analysis results of VFET with single-crystalline In2O3 channel formed with CAAC-IGZO seed.
figure 6

a HAADF-STEM image and (b) STEM-EDX profiles around the upper S/D electrodes. c HAADF-STEM image and (d) STEM-EDX profiles around the lower S/D electrode. e TEM image and (f) Fast Fourier transform (FFT) analysis results of a red square region denoted by 1 in (e). g Enlarged view of a blue square region denoted by 2 in (f). Regarding the STEM-EDX profiles, adequate quantities of Ga and Zn are detected between Upper S/D electrode 2 and ALD-In2O3, whereas only small quantities of Ga and Zn are detected between Lower S/D electrode 2 and ALD-In2O3. The fact that IGZO having crystallinity cannot be formed in a channel hole is consistent with the previously reported formation model of CAAC-IGZO39. Regarding FFT analysis results in the channel region, uniform FFT patterns were obtained continuously. The crystal orientations are aligned throughout the channel region.

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To confirm the effect of the seed, Fig. 7 shows a cross-sectional TEM image of the VFET in the case where the 2-nm-thick CAAC-IGZO film is not formed before In2O3 film formation. Unlike in Fig. 5, some grain boundaries are observed in In2O3 in the channel region in Fig. 7.

Fig. 7: Cross-sectional TEM image of VFET with In2O3 channel formed without CAAC-IGZO seed.
figure 7

a, b Images of the entire VFET. c, d Enlarged views of a red square region denoted by 1 and a blue square region denoted by 2 in (a, b). The channel-hole diameter is similar to that of Fig. 5. In the VFET formed without the seed, several crystalline particles with random orientation can be seen. The yellow dashed lines in (c, d) indicate the grain boundaries.

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Figure 8a–c show the comparison results of drain current (Id) versus gate–source voltage (Vgs) characteristics of FETs with/without the seed CAAC-IGZO film. The upper S/D electrodes were set to be “Drain”, and threshold voltage (Vth) was defined as Vgs at Id = 1 pA. With the seed, Ion at Vgs = 3 V was 28.8 μA, the standard deviation of Vth was 0.05 V (low), and the subthreshold slope (SS) was 86.7 mV dec.−1 (low). Without the seed, Ion was 22.5 μA, the standard deviation of Vth was 0.11 V, and SS was 95.7 mV dec.−1, which were inferior to those in the case with the seed.

Fig. 8: Evaluation results of electrical characteristics.
figure 8

Id–Vgs characteristics of VFETs with the In2O3 channels formed (a) with and (b) without a seed layer, c electrical characteristics list, and (d) measurement results of off-state leakage currents. For each channel region, a 10-nm-thick In2O3 film (Tsub = 200 °C) was formed via ALD under the condition where the oxidation time during which O3 flows was 9 s. The channel length (L) is defined as the interlayer insulator thickness.

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Next, we confirmed the off-state current. In the measurement of Id–Vgs characteristics of a single FET, the measurement limit of an off-state current is approximately 1 pA, and thus an off-state current below this value cannot be measured. Thus, we evaluated the off-state current using an evaluation circuit comprising the Device Under Test (DUT), a read circuit, and a write transistor40. For the DUT, 20000 VFETs with W/L = 60 nmɸ/95 nm were connected in parallel. The channel length (L) is defined as the interlayer insulator thickness. Lower S/D electrodes of each of the VFETs were connected to a storage node (SN). The evaluation results revealed that the off-state current of a VFET using single-crystalline In2O3 in its channel portion was 68.4 zA µm−1 at 85 °C, which was lower than that in the case without CAAC-IGZO (Fig. 8d). Evaluation by extrapolation revealed that the off-state current was 2.0 zA µm−1 at 27 °C, which was lower than that of a bulk Si FET67 by approximately 10 digits. That is, the In2O3 VFET also has a favorable off-state current. Figure 8a and d show that Vth showing normally-off characteristics (0.10 V) is obtained, and the on/off ratio with approximately 17 digits can be obtained at 27 °C.

Discussion

In this study, the formation of a single-crystalline In2O3 film was confirmed over an insulating film on an inner wall of a channel hole, which serves as a channel portion of a VFET, by utilizing CAAC-IGZO as a seed layer. We consider the principle of single crystallization of an In2O3 film on the insulating film as follows.

The In arrangement in the (001) plane of the CAAC-IGZO is similar to that in the (111) plane of the bixbyite crystal structure of In2O3. Thus, the lattice mismatch degree when the (111) plane of In2O3 is placed on the (001) plane of IGZO is low (0.55%) (Fig. 2a). Furthermore, the interface energy between the amorphous In2O3 and the (111) plane of the crystalline In2O3 is 1.92 eV nm−2, which is lower than that between the amorphous In2O3 and a plane with another orientation of the crystalline In2O3 (Fig. 2b). Accordingly, single crystallization of the In2O3 film in the channel region occurs in the following process:

(a) An In2O3 film is formed over and in a cylindrical portion of a VFET by ALD.

(b) Single crystallization of the In2O3 film over a CAAC-IGZO film serving as a seed layer occurs owing to solid phase epitaxy ((1) in Fig. 9)68,69,70.

Fig. 9: Schematic views of solid phase epitaxy of In2O3.
figure 9

Single crystallization of the In2O3 occurs on CAAC-IGZO seed (1) and progresses in the horizontal direction (2) and in the perpendicular direction (3).

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(c) Single crystallization of the In2O3 film progresses in the horizontal direction toward a region away from the CAAC-IGZO film owing to solid phase epitaxy, using the In2O3 film that has been single-crystallized in (b) as a seed layer ((2) in Fig. 9).

(d) After the solid phase epitaxy in the horizontal direction reaches an end portion of the In2O3 film, single crystallization of the In2O3 film progresses in the vertical direction with respect to the substrate plane owing to solid phase epitaxy, using the In2O3 film that has been single-crystallized in (c) as a seed layer ((3) in Fig. 9).

We infer that by single crystallization in such a manner, an In2O3 film having no grain boundaries in a direction where current flows was formed on the insulating film on the inner wall of the channel hole, which serves as a channel portion of the VFET.

In a VFET with an In2O3 channel formed using a CAAC-IGZO film as a seed layer, a current path in a channel portion has a single grain, and thus the same effect as that of an FET formed using a single-crystalline In2O3 can be obtained. TEM analysis confirmed that grain boundaries were not generated in the carrier path of the In2O3-based VFET formed using a CAAC-IGZO film as a seed layer (Fig. 5 and Fig. 6), and we also confirmed that Ion increase, Vth variation reduction, and SS improvement occurred in the VFET, compared to a VFET with an In2O3 channel formed without a seed layer (Figs. 8a and 8c). Accordingly, phenomena such as low Ion, Vth variation, and inferior SS are caused by grain boundaries across the carrier paths, and thus the elimination of grain boundaries in the channel region owing to solid phase epitaxy caused by the seed layer probably induces Ion increase, Vth variation reduction, and SS improvement.

A study of application of crystalline In2O3 to transistors was reported in 200745. In order to realize the application to LSI10, we formed a prototype of a high-integration vertical transistor suitable for 3D VLSI using single-crystalline In2O3 in its channel region. If the on-state characteristics of the single-crystalline In2O3 FETs are improved by, for example, reducing external resistance and on-state characteristics equivalent to those of n-channel Si FETs are obtained in the future, single-crystalline In2O3 FETs can be used in a manner similar to those of n-channel Si FETs used in VLSIs. This advancement can lead to further development in the field of VLSI via 3D integration. A CMOS circuit in which only a PMOS is formed over a Si substrate and an NMOS using single-crystalline In2O3 is stacked over the PMOS is expected to simplify a complicated process such as well separation (Fig. 10).

Fig. 10: Cross-sectional schematic views of CMOS.
figure 10

a Conventional CMOS and b 3D-CMOS that we propose. If all the Si FETs are PMOS FETs, the P-Well is not required for isolation, so that the Si FET process is simplified. In addition, the layout margin in the P-Well region can be reduced, so that the layout area can be reduced.

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We believe that a CMOS circuit using single-crystalline In2O3 FETs can achieve considerable power reduction owing to the implementation of 3D integration and their extremely low off-state current. If a CMOS circuit using single-crystalline In2O3 FETs is applied to supercomputers or servers, global power consumption is expected to shrink drastically. This advancement would therefore be a fundamental technique for combating global warming.

Methods

Sample fabrication process

We prepared a single-crystalline YSZ substrate containing Y2O3 at 10 mol% (Shinkosha Co., Ltd). Deposition of In2O3 was performed using a Picosun thermal ALD system (Model: R200). In the ALD process, the substrate was heated in a deposition chamber for 7 min, and the substrate temperature was kept at 200°C. One ALD deposition cycle was a sequence of In precursor (In(C2H5)3) for 0.1 s, a purge for 3 s, O3 + O2 for 9 s, and a purge for 3 s. The O3 concentration was 19 wt%.

Cross-sectional observation

The cross-sectional TEM images were captured with a JEOL JEM-ARM 200 F under conditions of an acceleration voltage of 200 kV, Cs-TEM, and magnification accuracy of ± 3%. HAADF-STEM and STEM-EDX analyses were performed with a JEOL JEM-ARM200F NEOARM. JED-2300T was used as a detector of STEM-EDX.

Simulation

Calculation of lattice mismatch of single-crystalline YSZ or InGaZnO4 (Fig. 2a) was performed in the following manner. We used Ogre 2.058, an open source code capable of generating an interface model between a bulk molecular crystal structure and a surface slab, and input data of a crystallographic information file (CIF), a bonding face, and structure characteristics of each crystal structure to calculate the lattice mismatch and the bonding cross-sectional area of each super-cell having two structures. Calculation of amorphous/crystal planes (Fig. 2b) was performed in the following manner: an interface structure of the amorphous/crystal planes was formed by molecular dynamics (MD) using LAMMPS software. M3Gnet was used in potential setting. A lower half of a cell was fixed, the temperature was raised to 5000 K, and an upper half of the cell was melted. After that, the structure was optimized (minimized). The whole cell was rapidly cooled down to 200 K and the interface energy was calculated from the equilibration energy by NVT ensemble. The interface energy was calculated by the following formula (2) where Eamorphous/crystal is the energy of the interface structure, Ecrystal is the energy of crystal, Eamorphous is the energy of amorphous, and S is the cross-sectional area of the interface.

$${{{\bf{Interface\; energy}}}}=\left({{{{\boldsymbol{E}}}}}_{{{{\boldsymbol{amorphous}}}}/{{{\boldsymbol{crystal}}}}}-{{{{\boldsymbol{E}}}}}_{{{{\boldsymbol{amorphous}}}}}-{{{{\boldsymbol{E}}}}}_{{{{\boldsymbol{crystal}}}}}\right)\div{{{\boldsymbol{S}}}}$$
(2)

Evaluation of electric characteristics

The Id–Vgs measurement was performed under atmospheric pressure at room temperature with a semi-automated prober (HiSOL, Inc.). A 4156 C parameter analyzer (Keysight Technologies) was used as a measurement instrument. The Id–Vgs measurement was performed under conditions of Vgs = −4 V to 4 V and drain voltage (Vds) = 0.8 V.

We evaluated the off-state current using an evaluation circuit comprising DUT, a read circuit, and a write transistor38. For the DUT, 20000 VFETs with W/L = 60 nmɸ/95 nm were connected in parallel. The lower S/D electrodes of each of the VFETs were connected to the SN. The evaluation was performed in the following manner: first, the write transistor was turned on, and a potential of 0.8 V was written to the SN; then, a potential of −1.5 V was continuously applied to gates of the DUT and the write transistor to maintain an off state; a change in SN potential (VSN) over time was measured through the read circuit, and the off-state current of the DUT was estimated.