Main

Unconventional practices of information processing in engineered materials have recently been explored, including mechanical computing that abstracts digital bits according to mechanism and material configurations17,18,21,22,23,24,25,26,27,28,29. For scalable computing capabilities, integrated circuits (ICs) are the conventional platform for computing digital electrical signals. Efforts are growing to embed mechanically strain-gated switching elements in ICs for the development of logic operations in soft matter19,20. By combining mechanical computing bit abstraction with reconfigurable electrical networks, ref. 30 realized all of the universal logic gates in soft and conductive mechanical metamaterials. Yet, a method to develop combinational logic ICs in soft materials has yet to be established. Mechanical computing networks are currently limited by the type and quantity of inputs that an output signal can drive20,30, and by the damping of the signal propagation in mechanical materials24,27. A design approach is required whereby scalable, higher-level computing operations are cultivated in soft, autonomous matter.

Inspired by the mathematical principles of switching theory for ICs31, here we introduce a robust strategy, grounded in Boolean mathematics, to guide the design of all combinational logic operations in soft, conductive mechanical materials. The approach builds on the logic gate components fashioned by ref. 30. We create an IC-synthesis procedure whereby any arbitrary combination of logic gates used in a combinational logic process can be realized. This facilitates information decoding and advanced arithmetic operations such as n-bit addition, subtraction, multiplication and magnitude comparators. These materials are programmed through a design process that supports automation through minimized sets of Boolean functions and multilayer monolithic fabrication techniques to increase computational density. We demonstrate reconfigurable IC materials that sense and process mechanical loading to compute higher-level n-bit arithmetic and decoding operations that could be used for intelligent response, actuation and communication.

The IC-synthesis strategy builds on the fundamental mechanical computing 1-bit-unit-cell material cross-section shown in Fig. 1a. When uniaxially compressed, a bifurcated kinematic collapse stage is reached with two possible compact configuration states that are controlled through left or right shear. A mechanics-based bit abstraction is exploited to represent the 1-bit mechanical shear input as ‘1’ for the anticlockwise (left shear) rotational state and ‘0’ for the clockwise (right shear) rotational state (Fig. 1a). A row of adjacent unit cells that are connected in parallel deform homogeneously with the same digital input owing to the mechanical disconnections between centre square tiles. To develop an n-bit material system with 2n unique configuration states, n unit-cell rows must be serially connected. For instance, a 2-bit material is shown in Fig. 1a with two mechanical input rows, A1 and A2.

Fig. 1: Bit abstraction through switching elements and gates.
figure 1

a, One-bit-unit-cell geometry with the 1 (anticlockwise) and 0 (clockwise) mechanical configurations to reach the corresponding self-contact states. The 2-bit material is also shown with two mechanical input rows connected in series, A1 and A2. ρ refers to the relative size of the unit cell having dimensions a and b. b,c, Schematic of the buffer (b) and NOT (c) elementary switches on a 1-bit unit cell with respective conductive networks. Digital mechanical inputs are highlighted in green. Digital electrical output terminals are highlighted in red with labels Q, electrical paths are marked as white lines and the circuits are powered by the cyan-coloured Vcc terminal. d, Schematics (top) and experimental images (bottom) of the AND and OR logic gates designed on a 2-bit material structure with their respective switching circuitry. e,f, The AND (e) and OR (f) gates shown in the four possible mechanical configurations with the appropriate digital outputs for each.

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Our embodiment of digital logic30 depends on the discrete mechanical behaviour of a unit cell coupled with an electrical network to develop two kinematic 1-bit switching elements. A mechanical material buffer switch (Fig. 1b) connects at the compact state to output an electrical digital signal QB of 1 when an input of 1 is applied, and yields an output QB of 0 for an input of 0. The second switch is a NOT switch (Fig. 1c): an inverted buffer switch with output QN. With the 2-bit material platform in Fig. 1a and electrical networks consisting of the buffer and NOT switches, ref. 30 realized all the fundamental 2-bit logic gates, namely AND, NAND, OR, NOR, XOR and XNOR. Figure 1d shows the implementation of the AND and OR gates on a soft urethane rubber substrate with conductive surface channels containing silver thermoplastic polyurethane (Ag-TPU) composites (see Methods for fabrication details). Figure 1e,f validates the four possible configurations for the AND and OR gates, respectively.

Leveraging the fundamental buffer and NOT logic gates30, Figure 2 illustrates the design process created through this work to program any higher-level combinational logic sequence in conductive mechanical networks. The process leverages the foundations of canonical Boolean functions and their algebraic combinations. A means to automate the mechanical-material design is given in Supplementary Information.

Fig. 2: Combinational logic design synthesis.
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a, The full adder logic diagram with the mechanical inputs (A, B and Cin) shown in green, and the electrical outputs (QSum and QCout) highlighted in red. b, The truth table corresponding to the full adder operation. c, A schematic illustrating the relationship between the QMSoP Boolean function minterms, and the 3-bit material columns that contain either NOT or buffer connected in series. d,e, A schematic (d) and experimental image (e) of the full adder material design that is constructed by connecting the material columns in parallel. f, Experimental digital output results of three possible configurations with their respective experimental images and schematics of the reconfigured network. Decimal inputs and outputs are shown at the top; binary inputs and outputs shown at the bottom. Connected paths that result in an output of 1 are highlighted in green or yellow. Electrical connections only occur through switches in the same column.

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To exemplify the design process established here, we use the full adder as a model logic combination. The full adder in Fig. 2a includes three digital inputs A, B and Cin. This logic operation adds the 1-bit numbers A and B, and allows for the 1-bit Cin input as a carry bit that is conventionally passed along in a parallel binary adder circuit. The full adder yields two digital outputs QSum and QCout, which correspond to the first-bit and second-bit digits in the binary number (QCoutQSum)2, respectively. Each output is a separate logic path in the design strategy created here. Thus, distinct truth-table outputs are obtained for a specific combinational logic process (Fig. 2b). The truth tables are utilized to extract the canonical standard sum of product (SSoP) Boolean functions for each output. An SSoP is devised of minterms containing the product (&) of all the input Boolean terms that are added together (|). Each Boolean term in the function corresponds to a switch in the circuit. Minimizing the SSoP corresponds to a reduction in the quantity of switches and, as a result, a reduction of the size of the mechanical material. The canonical function minimization Quine–McCluskey (QM) algorithm32 is applied here to the SSoP to obtain the reduced QSum and QCout QMSoP functions shown in Fig. 2c. Further details on the Boolean functions are presented in Methods.

We then employ the symbolic representation of switching circuits presented by ref. 31. In this approach, we construct the conductive network by utilizing the QMSoP functions composed using only the two elementary switches, buffer and NOT. As shown in Fig. 2c, each simplified minterm corresponds to a material column of three serially connected unit cells. An inverted term (′) corresponds to a NOT switch, and an ordinary term corresponds to a buffer switch. For instance, the initial minterm in the QSum function (A′ & B′ & Cin) contains two NOT switches on the A and B rows, and a buffer switch on the Cin row that are serially connected. Such a gate sequence is shown in the left column of the QSum in Fig. 2c. By this method, each simplified minterm is represented in a distinct material column, where the buffer and NOT switches are used in exact agreement with the QMSoP functions for a given combinational logic process. Then the material columns are connected in parallel as shown in Fig. 2d to form the IC material system. Both outputs arepowered by the same low voltage signal at the Vcc (cyan) terminal. The output terminals are separated to the QSum and QCout.

The mechanical IC material is then fabricated (Methods) with the full adder logic operation programmed on the surface as shown in Fig. 2e. This design is validated by the example addition arithmetic sequences shown in Fig. 2f. In practice, each layer undergoes shear and uniaxial compression to determine the digital input sequence (Methods). The column networks that electrically conduct and output a value of ‘1’ upon compaction are highlighted in yellow or green in Fig. 2f. As the conductive Ag-TPU ink is confined by the substrate geometry, electrical connections are only allowed through the switches in the same column. All eight addition computations possible for the full adder are exemplified in Extended Data Fig. 1 by simulated and experimental results.

The extensibility of this implementation is grounded in the generality of canonical Boolean functions coupled with the kinematics of the platform. Implementing this IC formulation requires (1) independent bi-state self-contact and (2) a reconfigurable mechanical-electrical network realized in the mechanical-electrical material unit cell. Thus, the mathematical foundation established here is not unique to the unit-cell geometry in Fig. 1a and may be generalized to other material platforms with the two features (1) and (2). Extended Data Fig. 2 introduces two alternative 1-bit-unit-cell geometries with the two features that ensure similar computing capabilities albeit with distinct mechanical force inputs.

To illustrate the scalability of our formulation, three fundamental 2-bit arithmetic operators are constructed with the QMSoP functions. These operators are the 2-bit adder, 2-bit subtractor and 2-bit multiplier, as shown in Fig. 3. The operators are applied between the two 2-bit binary operands, A and B, that are mechanically applied on the 4-bit material in the row order A1, B1, A2 and B2 from top to bottom. See Extended Data Figs. 3–5 for the logic diagrams for each arithmetic operator, respectively.

Fig. 3: Two-bit arithmetic operators.
figure 3

a–c, A chart illustrating the schematic and experimental images of the 4-bit material and computing network design for a 2-bit adder (a), a 2-bit subtractor (b) and a 2-bit multiplier (c). The operations are computed between two operands A (A2 A1)2 and B (B2 B1)2 that are mechanically entered (green) through the three representative material configurations. The binary digital outputs (denoted by Q in red font) for each configuration are compared with the decimal value for validation. The QBout binary digit in the subtractor output corresponds to a decimal value of −4.

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The 2-bit adder in Fig. 3a contains 32 electrical switches and 44 material unit cells. This is accounted for by 11 material columns each including 4 unit cells stacked vertically in series. By comparison, a 2-bit adder designed with the SSoP functions requires 60 switches and 64 unit cells. The Boolean function minimization through the QM algorithm allows for the same computing function with a significantly reduced quantity of switches. On the basis of the adder operation scalability analysis in Extended Data Fig. 6, the QMSoP reduces the material size by 31% in the 2-bit adder and by 92% in the 6-bit adder. For the specific material fabrications realized here, this corresponds to reduced mechanical energy stored per computing operation to achieve the compact state. Furthermore, a third method of designing combinational logic is created in this work, termed the substitution method (Supplementary Information). As shown in Extended Data Fig. 7, the 2-bit adder designed from the substitution method has 24 switches and 36 unit cells, which is still fewer than the number of switches and unit cells through the QMSoP. Yet, the substitution method is dependent on a sequence of manipulations to the switching circuit and is tedious to scale and automate compared with the QMSoP that exploits the canonical functions.

The QMSoP 2-bit subtractor shown in Fig. 3b contains 32 switches and 44 unit cells, which is the same quantity as for the QMSoP 2-bit adder owing to De Morgan’s theorem inversion of the switching network when a NOT gate is added to the logic diagram30 (Extended Data Figs. 3 and 4). Finally, the 2-bit multiplier shown in Fig. 3c requires 24 switches and 32 unit cells. With increasing n-bits, the order of the computational complexity governs the IC network and material size as shown through the scalability analysis in Extended Data Fig. 6.

These three, arithmetic-specific IC materials are fabricated (Methods) and experimentally validated through the representative arithmetic calculations shown in Fig. 3. The 2-bit adder and 2-bit subtractor result in three digital outputs corresponding to the binary numbers (QCoutQS2QS1)2 and (QBoutQD2QD1)2, respectively. It is important to note that the two’s complement binary representation is utilized for the 2-bit subtractor output, and thus the QBout binary digit corresponds to a decimal value of −4. The 2-bit multiplier results in four digital outputs that correspond to the binary number (QP4QP3QP2QP1)2. As shown in Fig. 3, the binary outputs for the three representative mathematical calculations agree with the decimal operations. See Extended Data Figs. 3–5 for all 16 possible mathematical computations able to be determined by the 2-bit adder, 2-bit subtractor and 2-bit multiplier, respectively.

We program an advanced mechanical IC material that communicates with a visual display (Fig. 4) to demonstrate the comprehensive sensing, information processing and response functionalities of mechanical IC materials. The corresponding logic diagram is shown in Fig. 4a, which includes 86 gates to govern 15 digital outputs. This operation contains four digital inputs: A1, B1, A2 and B2. The 2-bit number A is simultaneously added and multiplied with the 2-bit number B. The binary outputs are decoded to seven-segment number displays with a, b, c, d, e, f and g independent segments. As shown in Fig. 4b, the outputs corresponding to the addition and multiplication number are illuminated in red (a1, b1, c1, d1, e1, f1 and g1) and blue (a2, b2, c2, d2, e2, f2 and g2), respectively. Furthermore, the sum and product numbers are compared through a 4-bit magnitude comparator operation incorporated into the electrical switching network. Such operation results in three outputs, cm1 (<), cm2 (>) and cm3 (=) that govern each of the corresponding comparative symbols.

Fig. 4: Demonstration of the sensing, computing and actuating functionalities of a soft mechanical IC material.
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a, The logic diagram for the combinational operation with 4 mechanical inputs (A1 B1 A2 B2)2 and 15 electrical outputs. The operation includes a 2-bit adder, 2-bit multiplier, 4-bit magnitude comparator and two binary-coded decimal (BCD) 7-segment display decoders. b, A schematic illustrating the multi-input display with the number segments and comparator symbols that correspond to the independent computing material outputs. The number corresponding to the sum (A + B) and product (A × B) are illuminated in red and blue, respectively. c, A schematic of the programmed mechanical IC material that is constructed with five 4-bit layer assembly. d, Experimental image of the display set-up directly connected to the uncompressed computing material. A segment or symbol on the display is lit (ON) when the corresponding output is 1, and vice versa. e,f, Application of digital inputs to the mechanical IC material to enter the (0011)2 (e) and (0111)2 (f) arithmetic calculations show that the appropriate inequalities are displayed.

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A five-layer mechanical IC material with 137 switches is fabricated (Fig. 4c). As the digital outputs in a logic operation are independent of each other, it is possible to separate computing material layers that are networked by stacked assembly. The outputs are distributed in the material based on the QMSoP minterms to optimize the quantity of layers and unit-cell columns for specific force applications. Increasing the quantity of stacked layers decreases the quantity of unit-cell columns per layer. The network design for each of the 12 column layers can be found in Extended Data Fig. 8. According to the binary inputs, the current flow from the Vcc (9 V) source connects the appropriate light-emitting diode (LED) number segments and comparator symbols on the display. In Fig. 4d, the material initially has no digital input and correspondingly has no output. By manually applying a combination of uniaxial and shear traction, the (0011)2 digital input sequence is applied to all the layers. This corresponds to the decimal operations of (2 + 2)10 and (2 × 2)10. As shown in Fig. 4e, the material outputs the correct equality in the LED displays: 4 = 4. As these materials have volatile memory, the bit information is lost when the digital inputs are removed, which automatically resets the material. Further digital input of (0111)2 or corresponding decimal operations of (2 + 3)10 and (2 × 3)10 is then applied as shown in Fig. 4f to output the appropriate inequality through the LED displays: 5 < 6. See Supplementary Video 1 for demonstrations of the functionality of the mechanical IC material.

In Fig. 4, we show separated stacked layer assemblies that uniformly collapse while held in a material casing. Yet, monolithic material systems with multilayer logic operations that embed conductive networks through the material depth can reduce the quantity of unit cells and increase the computational density. Two fabrication techniques are demonstrated in Extended Data Fig. 9, which use casting and multi-material additive manufacturing methods to fabricate a 2-bit adder with 46% reduction in two-dimensional substrate area. See Methods for further fabrication details.

The formulation of combinational logic created here is grounded in Boolean mathematics31 and kinematically reconfigurable electrical networks33. Consequently, similarly complex and scalable information processing could be achieved in other length scales and in other physics where such principles may be harnessed. Therefore, the sense of ‘touch’ realized here could be augmented with a sense of ‘sight’ through photo-responsive hydrogels5 in the material system design process, or with a sense of ‘hearing’ through discretized spectral signalling like that used in the cochlea34. Certainly, the soft computing framework formulated here does not compete with the speed and complexity of conventional semi-conductor-based microprocessors. Yet, the information processing cultivated here is intrinsically scalable and sufficiently advanced to provision future engineered living materials with ample adaptability as they navigate the environment in pursuit of a programmed objective.

In this research, we introduce a robust strategy that exploits canonical Boolean functions and kinematically reconfigurable structures to program combinational logic into soft, mechanical IC materials. We demonstrate sensing, processing and responding functions in a monolithic material platform that thinks about digitized mechanical loading through higher-level combinational logic operations. Any arbitrary combinational logic process may be synthesized by this method and any degree of computational density may be achieved by the layer-by-layer fabrication approach. This foundation can be extended further by the formulation of analogue-to-digital conversion layers that help the materials to interface between the analogue mechanical loads natural to the environment and the requirement for digital sensory inputs. Nevertheless, as one embodiment of mechanical computing17, our approach offers advanced decision-making functionality and a roadmap for intelligence for researchers pursuing engineered living systems across a wide range of length scales.

Methods

Material substrate fabrication

The elastomeric material substrate is cast in a two-part mould. The mould components are designed in the computer-aided design (CAD) software SOLIDWORKS 2019 and three-dimensionally printed (FlashForge Creator Pro) with acrylonitrile butadiene styrene. When assembled together, the two-part mould realizes the negative of the material substrate shape with the appropriate networked channels for the conductive traces. The moulds used for the embedded network layer fabrication method include general gridded channels that may serve as a substrate platform for any 4-bit operation as shown in Extended Data Fig. 9b.

The channel cross-section for the conductive traces is 2.00-mm deep and 0.75-mm wide. The liquid urethane rubber (Smooth-On VytaFlex 60) material is mixed by hand for 3 min. Black dye (Smooth-On So-Strong) is added in the mixture (1% to 3% of the total urethane mass) to provide a visible colour contrast between the substrate and conductive path. The material is allowed to cure at room temperature for 16 h after being poured into the mould. The substrate is then demoulded and prepared for the conductive ink deposition. This moulding fabrication technique has been reported in previous studies30,35.

Conductive ink fabrication and deposition

After the urethane rubber substrate is demoulded, enamel-coated copper wire (22 gauge) is passed to each terminal surface through a 2.00-mm-diameter channel in the substrate depth. The enamel is removed from the extremities of the wires as they are utilized to power the networks (Vcc) and measure the digital outputs (Q) at the terminals. The wires are secured by applying a small amount of silicone adhesive (DAP All-Purpose) at the back surface. Using a 3.0-cc dispensing syringe with a 27-gauge needle, the Ag-TPU ink is then deposited in the channels and allowed to cure around the copper wires for 24 h.

A similar process is required for each independent layer in the embedded network fabrication method. For the latter case, after the Ag-TPU is cured on each independent layer, the layers are moulded together by applying a thin uncured coat of urethane rubber between adjacent layers. An additional mould is utilized to align and secure the layers together during the 16-h curing period. After careful demoulding, the layers behave homogeneously as a monolithic material.

The composition of the applied conductive ink is 35% (volume % (v%)) Ag microflakes (Inframat Advanced Materials, 47MR-10F) and 65% (v%) TPU elastomer (BASF Elastollan Soft 35A). Appropriate quantities of Ag microflakes and N-methyl-2-pyrrolidone (NMP) solvent are first mixed in a glass vial, and sonicated (Branson M2800 Ultrasonic Cleaner) for 60 min. TPU granules are then added to the Ag-NMP sonicated mixture, and planetary mixed (KK 300SS Mazerustar) at 2,000 rpm for 2-min increments. The planetary mixing process is repeated three times with gentle hand-stirring in between to ensure that the walls of the vial do not collect aggregates. The Ag-TPU is ready for deposition after the mixture has had 48 h for the NMP to evaporate at room temperature. This Ag-TPU fabrication procedure can be found in previous studies7,8.

Sample fabrication using additive manufacturing technique

To fabricate the 2-bit adder with the embedded networked layers, an additive manufacturing technique is explored that allows for the printing of the flexible substrate and conductive network simultaneously. The material and embedded network are designed as separate bodies in the CAD software SOLIDWORKS 2019. The conductive terminals extend to the back surface of the material to allow for power and output measurements. A dual extrusion fused deposition modelling three-dimensional printer (FlashForge Creator Pro 2) is utilized to print the substrate with non-conductive flexible TPU filament (NinjaTek Cheetah TPU) and the network with flexible conductive-carbon-based TPU composite filament (NinjaTek EEL TPU). After the printing process is complete, the material is ready for computation of mechanical input signals.

Experimental digital state characterization

The arithmetic operations used in the formulation of conductive mechanical IC materials such as the full adder, 2-bit adder, 2-bit subtractor, 2-bit multiplier and multilayer 86-gate operation are experimentally examined to validate the digital outputs with the corresponding truth tables. Each of the soft material systems is compressed to reach a specific compact state. A combination of shear perturbations during uniaxial compression controls the mechanical input or the configuration state that the material enters. This loading technique is shown in greater detail in Supplementary Video 1. Through this process, all the configurations are examined, and the digital outputs are measured at each state. A 5-V power supply is connected to the Vcc terminal through the enamel wires that power the conductive network, yet any voltage supply may be connected depending on the actuator. For instance, a 9-V supply is utilized to power the LED display in Fig 4 and Supplementary Video 1. Each of the voltage outputs Q are measured relative to a common ground utilizing a voltmeter (AstroAI DM6000AR). A voltage threshold near the Vcc of 5 V is considered a digital output of 1, and a voltage reading of 0 V is considered a digital output of 0 (ref. 30.)

QMSoP functions

This section describes the method utilized to obtain the QMSoP functions. The calculations here are exemplified on the full adder operation with two digital outputs QSum and QCout. Yet, such techniques are automated in this research and may be applied to directly obtain the QMSoP for all combinational logic operations. A canonical SSoP function is initially extracted from the truth tables for each digital output. An SSoP is devised of minterms corresponding to each bit output in the truth table. Each minterm contains the product (&) of all the input Boolean terms. If the input is ‘0’ in that specific configuration, the inverted term (′) is included in the product, and vice versa. All the minterms are added together (|) to form the SSoP form of the Boolean function. The SSoP functions for the QSum and QCout are described by equations (1) and (2), respectively.

$${Q}_{{\rm{Sum}}}(A,B,{C}_{{\rm{in}}})={A}^{{\prime} }\& {B}^{{\prime} }\& {C}_{{\rm{in}}}| {A}^{{\prime} }\& B\& {C}_{{\rm{in}}}^{{\prime} }| A\& {B}^{{\prime} }\& {C}_{{\rm{in}}}^{{\prime} }| A\& B\& {C}_{{\rm{in}}}$$
(1)
$${Q}_{{\rm{Cout}}}(A,B,{C}_{{\rm{in}}})={A}^{{\prime} }\& B\& {C}_{{\rm{in}}}| A\& {B}^{{\prime} }\& {C}_{{\rm{in}}}| A\& B\& {C}_{{\rm{in}}}^{{\prime} }| A\& B\& {C}_{{\rm{in}}}$$
(2)

As shown in equations (1) and (2), both QSum and QCout in the SSoP contain four minterms with A, B and Cin. The canonical function minimization QM algorithm32 is applied here to the SSoP. The modified QSum and QCout QMSoP functions are demonstrated in equations (3) and (4), respectively.

$${Q}_{{\rm{Sum}}}(A,B,{C}_{{\rm{in}}})={A}^{{\prime} }\& {B}^{{\prime} }\& {C}_{{\rm{in}}}| {A}^{{\prime} }\& B\& {C}_{{\rm{in}}}^{{\prime} }| A\& {B}^{{\prime} }\& {C}_{{\rm{in}}}^{{\prime} }| A\& B\& {C}_{{\rm{in}}}$$
(3)
$${Q}_{{\rm{Cout}}}(A,B,{C}_{{\rm{in}}})=B\& {C}_{{\rm{in}}}| A\& {C}_{{\rm{in}}}| A\& B$$
(4)

Using the QM algorithm, the QSum in equation (1) is already in the optimized canonical form. However, the QCout expression reduces significantly as shown by comparing equations (2) and (4).