1 Introduction

The utilization of renewable energy sources, namely solar energy, for distributed power generation has garnered significant interest due to the depletion of fossil fuels and the escalating levels of greenhouse gas emissions. Solar panels require series–parallel configurations, requiring appropriate power converters to generate high voltages [1]. Technological advancements, particularly in the applications require portability and photovoltaic arrays, require wide DC conversion ratios. Due to conductor losses, step-up transformers, and turn-on and turn-off times, conventional converters have a limited range of conversion ratios [2]. Fuel cells present potential substitutes but may result in a low DC voltage, complicating the controller design. Isolated dc-dc converters are undesirable for high-voltage gain applications, such as solar-powered systems, due to concerns like saturation, low efficiency, and large size [3]. Non-isolated topologies such as cascaded technology can resolve these issues. However, cascaded boost converters face issues of reverse recovery, instability, and high-voltage stress on the switches and diodes used in higher stages. Current-mode control is commonly employed to regulate switch-mode DC-DC converters; however, complex topologies such as quadratic converters may exhibit ambiguous behavior because of inner coupling and right-half side zeros [4]. Power converters frequently incorporate impedance networks to improve performance. To provide higher conversion rates and change the placement of additional capacitors and inductors for voltage gains, capacitors or inductors can be swapped. However, because impedance network synthesis is based on designer inspiration and experience, it introduces randomness and hinders the creation of new power converters. The computational complexity and lack of rationalization prevents the new converters to perform under various operating conditions for various applications [5].

Recent research articles proposed various transformer less and other converters in the context of improved voltage gain, reduced number of switches, multiple inputs, multiple outputs, reduced number of passive components, etc. Multistage DC converters were introduced for higher voltage gain, with higher number of switches [6] and multiple inputs [7]. They offered many advantages in contrast to their single-level counterparts, including higher efficiency, lower cost, and smaller size. Single switch multistage converters were introduced for high voltage conversion of low voltage sources, with large number of capacitors in the output stage [8]. Voltage multipliers, switched inductors, quadratic converters are the recent methodologies used in the DC converters for higher voltage gain and lesser switching stress [9, 10]. Raising of Electric Vehicles made several developments in the field of choppers. Introduction of bidirectional converters is one of the significant changes in choppers, used for battery charging not only in the normal conditions also in the fault conditions [11]. These topologies normally used to interface low voltage source to high voltage motor or any other load with bidirectional current flow capability [12]. However, they also had few drawbacks, such as the risk of imbalance between the different voltage levels and high switching stress [13]. Despite these challenges, multilevel DC-DC converters are becoming increasingly popular in a variety of applications, such as renewable energy generation, and power supplies for electronic devices [14]. Recent advancement in the DC-DC converters use voltage lift technique with reduced number of components. The converter achieved an increased voltage gain through a simple structure and provides free current ripple for the input source [15]. The output of the converter is enhanced using the voltage multiplier cell along with reducing switch count, voltage stress, and harmonic distortion [16]. SEPIC topology was used to settle quicker than other recent converters presented in recent literature at steady state voltage and current, reducing ripple values and ensuring stable output voltage and current [17]. The utilization of a solitary-driven semiconductor switch and inductor resulted in a substantial increase in voltage amplification, while maintaining a continuous input current and achieving a greater step-up conversion ratio. [10]. Modified Switched Inductor were used to reduce voltage stress across active switches. It provided higher efficiency with lesser cost [18]. Usage of Additional voltage boost capacitor provides more voltage gain with less stress across switch [19, 20]. Higher gain values also achieved using quadratic boost converter, double switched inductor and multiplier cells. These components also help reduce voltage stress on diodes and capacitors, as well as the size of the inductors [21, 22]. These topologies provide benefits such as reduced voltage stress on semiconductor devices, a lower number of devices required, increased power conversion efficiency, and a higher switch usage factor [23, 24].

This work presents a transformer-less non-isolated chopper that achieves a large voltage gain using only a single switch. The subsequent chapter provides a comprehensive explanation of the converter’s circuitry and a rigorous mathematical analysis. Chapter 3 outlines the criteria for selecting components and conducts a thorough assessment of the converter, comparing it to alternative topologies discussed in recent scholarly works. The final sections of the script contain the simulation and hardware findings, which serve to confirm the accuracy of the mathematical analysis of the converter Table 1.

Table 1 Evaluation of proposed topology with other BCss
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2 Circuit Diagram for Multistage Boost Converter

Figure 1 displays the comprehensive circuit schematic of the converter that has been proposed. The system consists of two distinct stages: the voltage multiplier stage and the voltage lifting stage. Initially, a diode and an inductor are linked in a sequential manner across the capacitor. This circuit has the capability to amplify the input voltage by a factor of two, depending on the values of the inductors. The second stage includes a switch SA, which regulates the output voltage based on the duty cycle. The voltage boosting stage comprises a sequence of self-compensating capacitors that are linked in parallel with the load to elevate the input voltage. The overall output voltage of the circuits is determined by the number of self-balancing capacitors (M) connected in the voltage lifting step.

Fig. 1
figure 1

Generalized circuit diagram of the multi-stage converter

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Circuit diagram of the two-stage converter shown in Fig. 2. It is derived from the generalized circuit, also having two stages. In the first stage, when VS is more than VA, diodes DS1 and DS2 are forward biased and capacitor CS1 charges, equal to VS1. When VA is more than the input voltage VS, diodes DS1 and DS2 are reverse biased and the capacitor CS1 discharges. Booster capacitor produces a voltage of 2VS, also responsible for the higher voltage gain provided by the topology.

Fig. 2
figure 2

Circuit diagram of a two-stage converter

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The output stage contains three diodes D0, D1 and DA to carry the capacitor current during charging and discharging. This stage also contains two output capacitors C1 and C2 and a voltage balancing capacitor CA. This setup balances the capacitor voltage during switch on and off conditions and provides a multi stage output across the load. Voltage across C1 is Vo,1 which is same as the output voltage of the multiplier stage (VA).

2.1 Modes of operation

Mode 1 (t0—t1): The passive components are selected for Continuous Conduction Mode (CCM) in such a way that the current value not falls to zero at any time. During this mode, Switch SA is tuned On and forms a closed loop for the current at the input side as shown in Fig. 3. Capacitor C1 discharges diode D1 to maintain the voltage balance at C1. Inductors LS1 and LS2 charge from the source, up to the voltage level VS.

$$V_{LS1} = V_{LS2} = {\text{V}}_{{\text{S}}}$$
(1)
$$V_{CS} = {\text{V}}_{{\text{S}}}$$
(2)

where, VLS1, VLS2 are the voltage across inductors LS1 and LS2 respectively. Capacitor CS also charges from the supply, so the voltage of the capacitor also equal to VS. Current ripples because of inductors LS1 and LS2 are described as,

$$\frac{{di_{LS1} }}{dt} = \frac{{{\text{V}}_{{\text{S}}} }}{{{\text{L}}_{{{\text{S}}1}} }}$$
(3)
$$\frac{{di_{LS2} }}{dt} = \frac{{{\text{V}}_{{\text{S}}} }}{{{\text{L}}_{{{\text{S}}2}} }}$$
(4)
Fig. 3
figure 3

Switch ON mode in CCM

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Mode 2 (t1—t2): During this mode of operation given in Fig. 4, switch SA in reverse bias condition and turned off. Inductors LS1 and LS2 discharges through diodes D0 and DA. Since the switches are blocked during this mode, the stress at the switches is equal to the capacitor voltage (V0,1) as shown in Fig. 5. Performance parameters of the components in this mode are given in (5)-(7)

$$V_{LS1} = V_{LS2} = \frac{{\left( {{\text{V}}_{{\text{S}}} + V_{CS} - V_{o} } \right)}}{2}$$
(5)
$$\frac{{di_{LS1} }}{dt} = \frac{{2{\text{V}}_{{\text{S}}} - V_{o} }}{{2{\text{L}}_{{{\text{S}}1}} }}$$
(6)
$$\frac{{di_{LS2} }}{dt} = \frac{{2{\text{V}}_{{\text{S}}} - V_{o} }}{{2{\text{L}}_{{{\text{S}}2}} }}$$
(7)

where VS is the source voltage. By applying V-s balance principle in (1) and (5),

$$DV_{S} + \left( {1 - D} \right)\left( {\frac{{{\text{V}}_{{\text{S}}} + V_{CS} - V_{o,1} }}{2}} \right) = 0$$
(8)
Fig. 4
figure 4

Switch OFF mode in CCM

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Fig. 5
figure 5

Voltages and currents during CCM

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The potential stress at output capacitor C1 can be derived as,

$$V_{o,1} = \frac{{2{\text{V}}_{{\text{S}}} }}{{\left( {1 - D} \right)}}$$
(9)

Similarly, the overall output voltage across the load, VO,M can be written as based on Fig. 1,

$$V_{o,M} = \frac{{2M.{\text{V}}_{{\text{S}}} }}{{\left( {1 - D} \right)}}$$
(10)

where, M is the number of output capacitors.

2.2 Discontinuous Conduction Mode

Similar to CCM, Discontinuous Conduction Mode (DCM) has first two modes of operation during the interval t0-td. During first mode of operation from 0 < t < D1T, under steady state conditions, average output current through the capacitor will be,

$$\frac{{2V_{S}^{2} D_{1}^{2} }}{{(2V_{S} - V_{O,1} )Lf_{S} }} = \frac{{2V_{O,1} }}{{R_{O} }}$$
(11)

So, from the operation of the converter during CCM given in (1)-(11), current flowing through the inductors LS1 and LS2 during mode-1 of DCM can be obtained as,

$$I_{L1} = I_{L2} = \frac{{DV_{S} }}{fL}$$
(12)

where, f is the switching frequency and LS1 = LS2 = L. During mode-2 operation of DCM, diodes DS1, DS2, D0 and DA are reverse biased as shown on Figs. 6 and 7. So, the current flowing through the inductors is forced to become zero at time td. Peak values of inductor currents are given in (12) when the switches are turned OFF.

$$I_{L1} = I_{L2} = \frac{{\left( {\frac{{V_{o} }}{2} - V_{S} } \right)D_{c} }}{fL}$$
(13)
Fig. 6
figure 6

Switch OFF mode in DCM

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Fig. 7
figure 7

Voltages and currents during DCM

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Load is supplied by the capacitors C1 and C2, then the output voltage becomes,

$$V_{o} = - \left( {V_{C1} + V_{C2} } \right)$$
(14)

From (11)-(14), duty cycle of the DCM can be calculated as,

$$D_{c} = \frac{{2V_{S} D}}{{V_{o} - 2V_{S} }}$$
(15)

By considering the average current in the capacitor and DC,

gain value of this mode is,

$$G_{D} = \frac{{V_{o} }}{{V_{S} }} = 1 + \sqrt {1 + {\raise0.7ex\hbox{${D^{2} }$} \!\mathord{\left/ {\vphantom {{D^{2} } \tau }}\right.\kern-0pt} \!\lower0.7ex\hbox{$\tau $}}}$$
(16)

where, fs = 1/T and LS1 = LS2 = L. By solving the equation, the time constant \(\tau = \frac{{Lf_{S} }}{{R_{O} }}\) will be

$$\tau = \frac{{D\left( {1 - D} \right)^{2} }}{4}$$
(17)

Based on the value of \(\tau\), the boundary between DCM and CCM with respect to various duty cycles is shown in Fig. 8.

Fig. 8
figure 8

Tou region for various duty cycles

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3 Selection of Components

3.1 Voltage Stress Across Devices

Higher voltage stress leads to more complexity in the design and increases the cost of the device. Voltage stress across the device is the essential parameter to select a device. Voltage stress across the device is the function of current flowing through the device. Average value of inductor currents ILS1 and ILS2 are given in (24) and (25),

$$I_{LS1} = I_{LS2} = \frac{{2I_{o} }}{{\left( {1 - D} \right)}}$$
(18)

Based on the operating modes discussed in Fig. 5, Voltage stress across switch is given by (26)

$$V_{SA} = \frac{{V_{o} }}{2}$$
(19)

where, VSA is the potential stress across the switch SA. Referring to Fig. 6, when diode DS1 and DS2 is blocked the potential stress is equal to VC1-VS. The Voltage across the diode DS1 and VS2 is,

$$V_{DS1} = V_{DS2} = V_{C1} - V_{S} = \frac{{\left( {1 + D} \right)V_{S} }}{{\left( {1 - D} \right)}}$$
(20)

Similarly, voltage stress across D0 (VD0) equals to output voltage and given in (21).

$$V_{D0} = V_{C1} = \frac{{V_{o} }}{2}$$
(21)

3.2 Selection of Inductors

Critical values of inductances are calculated using the minimum inductance calculation method from CCM operations. Referring to Fig. 4, change in inductor current ILS1 is obtained as

$$\Delta I_{LS1} = \frac{{DTV_{S} }}{{L_{1} }}$$
(22)
$$I_{LS1min} = I_{LS1} - \frac{{\Delta I_{LS1} }}{2}$$
(23)

From (34), (35) and (25), minimum value of inductor LS1 can be calculated as,

$$L_{S1} \ge \frac{{D\left( {1 - D} \right)^{2} R}}{4f}$$
(24)

Concerning Figs. (3) and (4), current flowing through the inductors in both modes is same. So, the value of inductor LS2 is equal to LS1.

3.3 Selection of Capacitors

Selection of capacitors is also an important factor in the DC-DC converter design that provides a better voltage gain and stability. From Figs. (3) and (4), change in charge and voltage ripple across the capacitor is,

$$\Delta Q_{S} = C_{S} \Delta V_{CS} = DTI_{LS1}$$
(25)
$$\Delta V_{CS} = \frac{{DTI_{LS1} }}{{C_{S} }}$$
(26)

(25) and (26) provide the relationship between the capacitance value, voltage ripple and the switching frequency f. Minimum value of CS is given by

$$C_{S} \ge \frac{{DI_{o} }}{{\left( {1 - D} \right)f\Delta V_{CS1} }}$$
(27)

Which is the function of voltage ripple across CS given in (40) and switching frequency f.

3.4 Comparison with other Topologies

The multistage DC boost converter presented in this manuscript is compared with other topologies presented in the recent literature. Some of the key parameters like Overall Gain, Number of passive and active devices, voltage stress across the switch and Gain value with respect to Total Component Count (TCC). The gain value of the converter is greater than the topologies described in [10, 15, 19] and [21]. The voltage across the switch is better than all topologies even gain value is lesser than some of the topologies presented. [17,18,19] have posted exponential voltage gain with higher number of components and poor gain to TCC ratio. The pictorial representation of the voltage gain is presented in Fig. 9, in which the gain of all the topologies are plotted with respect to duty cycle. The proposed topology posted higher gain value. The corresponding gain to TCC ratio with respect to duty cycle is plotted in Fig. 10. Figure 11 shows the overall efficiency comparison of the topology for various load condition. All the topologies compared in this scenario provide higher efficiency in which the proposed topology registered better efficiency over most of the recent topologies. The proposed topology produces a maximum efficiency of around 93% at 200W, only [22] has better efficiency than other topologies at this load. It is observed that the presented topology has better parameters in overall, which could be a good alternative for the existing power converter for modern applications.

Fig. 9
figure 9

comparison of gain with respect to duty cycle

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Fig. 10
figure 10

comparison of gain to TCC ratio with respect to duty cycle

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Fig. 11
figure 11

comparison of efficiency with respect output power

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4 Results and Discussion

4.1 Simulation Result

The modes of operation and mathematical representation discussed in previous chapters are verified with Matlab/Simulink tool. The simulation results are presented in this section to prove the mathematical analysis of the system. The system is simulated with active and passive components values analysed in previous chapters.

An input voltage of 20 V (VS) is considered, and the resulting voltage across the load in the converter is displayed in Fig. 12. The frequency at which the switching occurs is 20 kHz, and a load with a resistance of 100Ω is being taken into account. In terms of the design specifications, the circuit incorporates passive elements such as LS = 50mH, CS = 200μF, and output capacitors with a capacitance of 400μF. The converter's overall output voltage V0,2 is measured at 150 V, which deviates from the theoretical output voltage of 160V. The output voltage stabilizes at a time of 0.04 s with a maximum value of 220 V, falling inside the allowed range.

Fig. 12
figure 12

Output voltage at CCM

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The corresponding output current of the presented circuit is shown in Fig. 13. The output current is found to exhibit a direct correlation with the overall output voltage and stabilizes at a value of 1.6A, which makes the overall power of the system around 240W. This is slightly lesser than the described power of 250W.

Fig. 13
figure 13

Output current at CCM

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The inductor values have chosen for the CCM operations were explained in chapter 3. Figure 14 shows the inductor current at CCM, which also describes the current oscillates between a minimum value of 1.8 A and a maximum value of 11A. The value of inductor current oscillates around 6A, satisfies the design parameters for CCM operation. It is also observed that, since the inductor values are equal the inductor currents are equal. The capacitor voltage is shown in Fig. 15. The voltage across the input capacitor is 18 V, lesser than the input voltage by minimum value.

Fig. 14
figure 14

Inductor current at CCM

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Fig. 15
figure 15

Voltage across the capacitor CS at CCM

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The presented circuit is being analyzed using inductors of different values as well. While the voltage and current levels at the load remain comparable to the previous mode of operation, the current flowing through the inductors varies depending on the specific inductor values, as seen in Fig. 16. This condition arises when the value of LS1 exceeds that of LS2, but both currents have identical minimum and maximum values and similar durations for charging and discharging.

Fig. 16
figure 16

Inductor current at CCM when L1 greater than L2

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The proposed multistage DC converter analysed with DC mode to verify the mathematical analysis. Figure 17 shows the output voltage of the circuit at DCM. Though the settling time is similar to CCM, amplitude increases to 165V. The corresponding load current value shown in Fig. 18, settles at 1.6A. This makes the overall power of the circuit as 260W, higher than the designed value.

Fig. 17
figure 17

Output voltage at DCM

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Fig. 18
figure 18

Output current at DCM

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Figure 19 shows the inductor current at DCM, which also describes the current oscillates between zero and a maximum value of 16A. The value of inductor current oscillates around 8A, satisfies the design parameters for DCM operation. The voltage across capacitor CS during DC mode shown in Fig. 20. As per the design of the circuit the voltage across the capacitor equal to the input voltage of around 18V.

Fig. 19
figure 19

Inductor current at DCM

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Fig. 20
figure 20

Voltage across the capacitor CS at DCM

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Theoretical and simulated values are compared, and the findings are presented in Fig. 21. The overall gain value of the proposed two stage DC converter exhibits exponential growth as the duty cycle increases. The output voltage increases correspondingly, as it is directly reliant on the input voltage.

Fig. 21
figure 21

Comparison of Theoretical and simulation values for various duty cycles

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Overall efficiency of the circuit for various duty cycles is presented in Fig. 22. It shows the efficiency increases at the first half of the duty cycle and reduces during the second half of the duty cycle range. The maximum efficiency of the converter is achieved over D = 0.4. It is also observed that the overall losses occurred at the converter is minimum at this point, with a gain of 6.67, as described in chapter 3.

Fig. 22
figure 22

Efficiency value for various duty cycles

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4.2 Hardware Results

The hardware prototype of the presented topology shown in Fig. 23, was developed to verify the simulation results presented in previous section. The prototype has a IRF840mosfet for switching, the FPGA Spartan kit was utilized to generate a gating pulse. The passive components are utilized as do in the simulation. Figure 24 displays the input and output voltages of the system when a gate pulse is applied. The converter yields a total output voltage of 140 V when provided with an input of 20 V. The prototype's overall gain value is 7, which is lower than the theoretical value. The voltage across capacitor C1 is 70 V, which exhibits an equivalent gain value for the initial stage.

Fig. 23
figure 23

Hardware prototype of the proposed converter

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Fig. 24
figure 24

Input and output voltages of the proposed circuit

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The potential stress across across the switch SA is presented in Fig. 25. Switching stress is reduced to zero when turned on and increases when turned off. It is observed that the switching stress value is around 80V which is almost equal to the capacitor voltage V0,1. The capacitor voltage is also presented in the figure for comparison. The overall switching stress of the converter is less when compared to output voltage. This is always constant even though the number of output stages increases.

Fig. 25
figure 25

Voltage stress at the switch and capacitor C1

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Figure 26 shows the current values flowing through the inductors LS1 and LS2. It is observed that the inductor charges when the switch is ON and discharges during switch OFF condition. The minimum and maximum value of inductor current ILS1 is 4A and 10A respectively, shows the experimental results follows the simulation results as the current oscillates at 7A. The current through inductor LS2 oscillates between 4 and 9A, describes the inductor values are equal and the circuit operates at Continuous Conduction Mode.

Fig. 26
figure 26

Inductor currents and gate pulse

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Voltage across inductors LS1 and LS2 depicted in Fig. 27. As mentioned in the previous sections, voltage across the inductors are equal to the input voltage. The hardware output satisfies that the voltage across the inductors are around 20V, equal to the input voltage. It is observed that the hardware results prove the effectiveness of the circuit as do in the simulation. This topology could be an effective alternate for the existing DC-DC multistage converter topologies and the results proved it.

Fig. 27
figure 27

Inductor voltages and gate pulse

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5 Conclusion

A transformer-less multistage boost DC-DC converter with modified voltage doubler circuit was discussed in this manuscript. This topology has two stages as the first stage gave a significant boost to the input voltage and the second stage lifted the voltage based on the number of stages. This topology has various advantages like high voltage gain, fewer passive components, and less voltage stress. The model was analysed in both continuous conduction mode and discontinuous conduction mode with equal and unequal inductance values. Despite the difference in values between the two inductors, the proposed converter exhibits good performance and easy control. The performance parameters were also presented along with the current and voltage waveforms. Performance of the presented model was verified in continuous conduction mode with a hardware prototype and the results were presented. This converter can provide a voltage gain of around 8 for two output stages, with lesser potential stress at the switch. It is suitable for low power applications with no additional switches and isolated gate-driving circuits.