Introduction

Reconfigurable computing is an architecture deal with the flexibility of high performance of hardware and software components by processing with computing platforms like Field-programmable gate arrays (FPGAs). They are reprogrammed to specific application based on their functionality needs after manufacturing. This characteristic of FPGAs differentiates from ASICs, which are designed for a particular application or task [1]. FPGAs find their usage in widely different fields, where their reprogrammable ability renders various benefits over ASICs implementations [2, 3]. This capability of FPGAs permits hardware designs to upgrade or reuse after implementation. When compared to ASICs or full-custom design, FPGAs offer many advantages, which include the low cost in the silicon chip area, an increase in its performance and low power consumption [4]. On the other hand, vendors of these FPGAs include Xilinx, Altera, and Atmel are analyzed, and they are compared by various parameters.

The architectures of reconfigurable systems can be divided into two categories depending on their granularity which are fine-grained and coarse-grained architectures. These architectures are configured by parallelism such as bit-level and word-level, respectively. The coarse-grained reconfigurable systems provide effective area utilization, low power consumption and efficient performance compare to fine-grained systems. The other important aspect is partial reconfiguration (PR) which defines the process of modifying one or multiple portions of the logic blocks while the other sections are unchanged. PR is favorable for embedded hardware systems, because these systems are adjustable to computation in different conditions while processing data.

This paper is summarized in this way: In “FPGA as a Reconfigurable Architecture” section, it gives a general view of FPGA architectures and types of FPGAs. “Fine-Grained Reconfigurable Architectures” and “Coarse-Grained Reconfigurable Architectures” sections include fine-grained and coarse-grained architectures, respectively. In “Partial Reconfiguration” section, it explains partial reconfiguration and some examples. Finally, the survey concludes with the wide area of applications of reconfigurable computing are mentioned in “Applications” section.

FPGA as a Reconfigurable Architecture

FPGAs provide better reconfiguration in which bit-level configuration is performed. The common FPGA architecture includes an array of programmable logic blocks which implement digital logic functions. The reconfiguration can be classified into two modes. They are static and dynamic reconfiguration. The configuration of the reconfigurable unit is performed only one time and cannot be modified when the task is running is known as static or compile-time reconfiguration. In dynamic reconfiguration, the configuration can be changed during the course of execution. The reconfiguration time should be minimized to enhance the overall performance of the reconfigurable processors when compared with that of general-purpose microprocessors. The minimization of reconfiguration time needs to be focused on [5]. FPGAs also support implementation level reconfiguration which offers several product families by suppliers like \(\hbox{Xilinx}^{\textregistered }\), \(\hbox{Intel}^{\textregistered }\) \(\hbox{Altera}^{\textregistered }\), etc. In FPGA architecture, a logic block consists of few logic cells made up of Look-up tables (LUTs), full-adder and D-flip flop as shown in Fig. 1.

Fig. 1
figure 1

Structure of a logic cell

Full size image

The architecture of FPGA composed of three major constituents such as programmable logic blocks, programmable routing (interconnects) and Input/Output (I/O) blocks.

Programmable Logic Blocks

The programmable logic block gives basic computational and some storage elements which find their applications in digital logic systems. A basic logic element (LE) comprises of programmable combinational logic, a flip-flop and a carry logic for reducing delay and area cost. Recent FPGAs contain various combination of blocks such as multiplexers and dedicated memory blocks. Configuration memory is needed for these programmable logic blocks to perform any specific task of each LE [1]. These logic blocks require routing channels to connect each other and I/O blocks to interface with external signals.

Programmable Routing

The programmable routing architecture comprises of pre-manufactured programmable wiring segments and switches which are organized in horizontal and vertical routing channels. It provides a connection between logic blocks and I/O blocks. In routing architecture, hardened multiplexers are used to save the SRAM cells and pass transistors are used for the connection of output pins. They are used to bring logic elements together like clusters [4]. The programmable logic elements are connected by interconnecting resources. Generally, these resources are configurable, because the signal path can be determined during compile or run time before the time of fabrication. This flexibility of interconnection between logic blocks can be used for mapping the reconfigurable hardware with a variety of circuit structures based on their requirements.

Fig. 2
figure 2

A general structure of island architecture

Full size image

There are primarily four global routing architectures: Island, Cellular, Long-line, and Row. In island architecture, configurable logic blocks (CLBs) look like islands surrounded by routing interconnect, as shown in Fig. 2. CLBs are gridded on a 2D mesh-like structure. The programmable routing network connects I/O blocks around FPGA chip.

Programmable I/O

The logic blocks and routing architecture to the external components are interfaced by using programmable I/O pads. The I/O pads are surrounded by a logic circuit which form as I/O cells which occupy a large area of the FPGA’s total utilization. Because of variations in the voltages (input voltage and reference voltage), the complexity of the design of I/O programmable blocks is high. It is important to select the design standards of I/O architecture [1] and these standards support for increasing the required silicon chip area for I/O cells. The development of FPGA architecture results in the addition of more dedicated programmable function blocks. These blocks contain up to four I/O elements (IOE). They are partitioned into two categories. They are two row I/O blocks for row interconnects and column I/O blocks for column interconnects.

Fig. 3
figure 3

FPGA architecture

Full size image

The I/O Blocks in Xilinx Virtex FPGA are arranged in groups on the periphery of the device which can be used independently, or they can be combined in the group connected directly to a switch matrix [2] as shown in Fig. 3. The special functional blocks like ALUs, embedded processors, memories, multiplexers, generic DSP blocks have been added to the FPGA based on the requirement for various applications.

Anti-Fuse-Based FPGAs

FPGAs use anti-fuses are having two terminals which are connected to inner and outer layers of antifuses, and a dielectric is kept in between these layers as shown in Fig. 4. Initially, there is no current flow between the layers due to the resistance of the dielectric is high. The power dissipation is large when high voltage is applied, which affects the dielectric and results in melting it. This process significantly decreases the resistance, and a permanent link will be formed and connects the two layers [6]. Since anti-fuses can be built using modified CMOS technology, they are very much suitable for FPGAs [7].

Fig. 4
figure 4

Actel PLICE antifuse

Full size image

The most important advantages of the anti-fuse chips are small area utilization, low resistance-capacitance (RC) delays in the routing process, low resistance, and parasitic capacitance. This type of FPGAs cannot be repeatedly reprogrammed. Hence, they are otherwise called as one-time programmable FPGAs since they are programmed once by the user and cannot be changed anymore.

SRAM-Based FPGAs

SRAM cells are used to store configuration data and program the routing interconnect. In SRAM-based FPGA, the output of SRAM Cells can control the functionality bits of the logic blocks and their interconnections [6]. The configuration of the logic blocks and the connection can be done by Static RAM (SRAM). These FPGAs may include in the boards of Xilinx (Spartan and Virtex families), Actel (now Microsemi), Lattice, QuickLogic, Atmel and Altera (FLEX, Stratix, and Cyclone). The foremost feature of SRAM-based module is that FPGAs can be reprogrammed or configured numerously. The value assigned to the SRAM cells can be changed to make a new connection or a new function. The complexity of this technology is SRAM cells occupy a large chip area. Since the device is volatile, the data stored in the static memory is not available if there is a power failure [8]. To keep the configuration data and store it into the FPGA-device, non-volatile memories or external sources are required at every power-up.

Flash-Based FPGAs

These types of FPGAs use flash as a major source for configuration storage, and there is no need for SRAM. The main advantage of the flash-based FPGAs is their low power consumption. The radiation effects do not affect the performance of Flash-based FPGAs. Some of the devices support this technology may include Actel(Igloo and ProASIC3), Xilinx (XC2C Family, XC95 Family), Lattice (Mach X02, Mach XO, LFXP, iSP Mach), Altera ( Max V, Max II) and Atmel ATF families. In Flash-/EEPROM-based programming technology such as Actel ProASIC chips, there is a floating gate between the two transistors stores the programming information. There is a sensing transistor which is used to write and verify the voltage of floating gate while the other is the switching transistor, which is used to erase the floating gate. Table 1 shows the power comparisons of flash and SRAM-based FPGAs.

Table 1 Comparisons of power parameters for flash- [9] and SRAM-based FPGAs [10]
Full size table

Fine-Grained Reconfigurable Architectures

Fine-grained reconfigurable architectures (FGRAs) comprise of Look up tables (LUTs) made up of a small number of logic blocks. These architectures provide better performance and high flexibility based on the amount of complexities in the bit-level configuration [12]. Programmable Logic Devices (PLDs) support these fine-grained architectures since logic blocks are as small and simple as the macro cells. Atmel AT40K is the best example for fine-grained architecture made up of small identical cells with an array of 4 x 4 sector size arranged symmetrically, as shown in Fig. 5. It consists of 8-sided core cells, and they are connected to each other in all directions. These small cells in this architecture execute Boolean functions and provide greater functionality based on the requirements. [13]

Fig. 5
figure 5

ATMEL AT40K

Full size image

The logic block in this architecture consists of logic elements and some flip-flops. The logic elements require more number of data bits for configurations, since the array of symmetrical cells has several configuration points to perform small computations [13]. These programmable logic blocks are useful for image processing, decoding, and encryption [14].

Fine-grained dynamically reconfigurable (FDR) devices composed of a large number of identical reconfigurable LEs which ensure configuration into LUTs and interconnects randomly. The configuration improves the flexibility of allocation of hardware resources between interconnects and LUTs considerably based on its requirements.

The drawbacks of FGRAs are large routing area, reduced clock speed, huge configuration data, poor area utilization and reduction in bandwidth, etc. Some of the major setbacks are listed below.

Low performance and high power consumption: The configuration logic blocks (CLBs) are connected by programmable switch boxes for the formation of word-level modules. This leads to a decrease in performance and power consumed by the device is quite high. [15]

Large configuration context and time: The amount of time required for configuration is high for more number of configuration bits. If the configuration is at the bit level, individual configuration signals can be applied to every CLBs and interconnecting wires. This shows more configuration context should be transferred from the memory and therefore configuration time is increased. When reconfiguration are required frequently, the large reconfiguration time may degrade the performance [4].

Large routing overhead: The interconnection of CLBs increases routing overhead to form a word-level parallelism or datapath functions[12].

Poor area utilization: As CLBs are not suitable for performing logic operations, they are used to pass signals to each other for routing purposes. Generally, FPGAs available at commercial market utilized nearly 90 percent of the chip area for routing resources [16].

Huge context memory: The requirement of context memory is also increased due to the large reconfiguration contexts and complex datapath functions. So external memories are used to store the reconfiguration context. This will further increase the reconfiguration time (Table 2).

Table 2 Comparison of types of FPGAs [11]
Full size table

Coarse-Grained Reconfigurable Architectures

Coarse grain reconfigurable architectures (CGRAs) encompass functional units (FUs) arranged like a mesh-type network, programmable interconnecting wires, and memory (Table 3). Unlike the fine-grained programmable logic, blocks are incapable of controlling the functions, and the coarse-grained logic blocks can perform multiple bit datapath and complex operations. CGRAs have several advantages when compared with FGRAs [17].

Table 3 Different types of devices based on configuration
Full size table

Minimal configuration contexts and time: The interconnections are configured efficiently by control (configuration) bits in the configuration memory. The coarse-grain reconfigurable units (CGRUs) require very fewer control bits for the specific operations. Since interconnecting wires are configured at datapath level, a few control bits are required to set up the interconnection among the units. The reconfiguration time is very much reduced as a result of the low configuration context, which allows coarse-grain reconfigurable systems to find their uses in various purposes [15].

Reduced context memory size: Being coarse-grained in nature, CGRAs acquire small configuration context overhead. The context memory size is reduced concerning the reduction in configuration contexts. The switching of configuration from one to other with minimum context overhead permits the usage of configuration memory efficiently.

Increase in performance and low power consumption: Since the design of interconnections is optimal and the implementation of CGRUs is hardwired, the performance of CGRUs is high, and power consumption is also low.

Area efficiency and decrease in routing overhead: CGRUs are permanently connected units for specific designs. They are not designed by the combination of CLBs and interconnecting wires, ensuring reduced routing overhead and area utilization is also improved [13].

Marco Lanuzza et al., presented MORA (Multimedia Oriented Reconfigurable Array) a new approach of CGRA, especially for multimedia processing applications. This reconfigurable system has been designed for offering effective support to basic arithmetic functions, extensive bandwidth and memory resources is dispersed efficiently [18].

Becker et al., implemented a new architecture for coarse-grained dynamically reconfigurable hardware architecture called DReAM (Dynamically and Reconfigurable Hardware Architecture for Mobile Communication Systems) for wireless communication systems to achieve the required aspects for mobile communication [19].

CGRAs try to solve the flexibility and routing overhead by supplying complex operators and multiple-bit wide data paths at the bit-level configuration. In silicon, the wide datapath permits the implementation of complex operators efficiently. The complex operators from bit-level processing units are removed by generating the routing overhead [20]. FGRAs are more flexible than CGRAs [13], but CGRAs are easier to program, and reconfiguration is faster. CGRAs can be categorized based on the positioning of processing elements such as Mesh-based [21, 22], linear arrays based [23, 24], Crossbar-based architectures [25], etc.

Partial Reconfiguration

Partial reconfiguration (PR) is defined as the modification of logic blocks by transferring partial bit files, whereas other parts of circuitry continue to run without any interruption. Instead of full reconfiguration, partial reconfiguration is required when configurations do not employ the entire reconfigurable device entirely, or only a part of it needs alteration. There may be different configurations performed in the hardware areas when configurations do not utilize the entire area accessible inside the range. PR can be partitioned into static and dynamic depending upon their functionalities. In static PR, FPGA becomes active only during the process of reconfiguration. Although some of the data is redeployed to the device, remaining part of the device is inactive and becomes active when the configuration is finished. Dynamic (active) partial reconfiguration which enables the portion of the device to be modified or configured when the remaining parts of FPGA are still operating.

Partial reconfiguration can be performed through either an internal host residing in the core logic, or as an external host via dedicated device pins. The advantage of the internal host is that it stores all the logic needed to perform PR on the device, without the need for external devices [26].

Partial reconfigurable hardware architectures can support for increasing entire reconfiguration flexibility, reducing power consumption and efficient utilization of FPGA and these architectures are employed in Xilinx Virtex families (Kintex-7, Artix-7, Virtex-4 to Virtex-7) and the SoC family(\(\hbox{Zynq}^{\mathrm{TM}}\)-7000) [27, 28]. PR can minimize the amount of data configuration which should be loaded into reconfigurable hardware [29].

Xilinx initially proposed two categories of PR are module-based and difference-based methodologies [30, 31] followed by the Early Access Partial Reconfiguration (EAPR) flow. Module-based partial reconfiguration allows reconfiguring different modules at the time of design specification. Difference-based partial reconfiguration can perform only a few changes to the design parameters. The EAPR flow is an approach which permits signals to cross over the boundaries of the partially reconfigurable area and maintains 2D reconfigurable rectangular module shapes. Since there are no constraints in EAPR flow, it helps in fixing the problems raised in the modular design methodology. The main goal of EAPR flow is some parts of the FPGA remains stationary, while remaining parts are dynamically reconfigurable during execution. This flow uses Bus macros (BMs) to ensure a connection can be done properly between static and dynamic reconfigurable modules during the process of reconfiguration [32]. The Internal Reconfiguration Access Port (ICAP) is a configuration port which allows accessing the FPGA configuration memory at the time of execution [33]. The ICAP is available in almost every Xilinx FPGAs from basic to advanced device architectures [34]. In Virtex-II series, the ICAP provides an 8-bit I/O data buses with the input clock. ICAP configuration is upgraded in Virtex-4 Series with high bandwidth (32-bit I/O data bus) [35]. An embedded soft-core processor such as \(\hbox{PowerPC}^{\textregistered }\) or \(\hbox{MicroBlaze}^{\textregistered }\) can be implemented in the fabric of FPGAs to control dynamically reconfigurable system [36]. ICAP provides better solution for user-defined applications.

Virtex devices support dynamic reconfiguration without any interruption, when a configuration bit holds the same value before and after reconfiguration, there is no disruption in operation from the resource controlled by that bit without the inclusion of LUT RAMs and Shift Registers (SRL16). This constraint was removed in the Virtex-II/Pro FPGAs and Virtex-4 devices by introducing EAPR flow tools.

Z.Xiao, et al., explained the new Altera partial configuration flow and identified the problem of a wide range of sizes for partial reconfiguration bitstream [37].

Vipin et al., addressed the major role of partial reconfiguration in Xilinx Zynq which comes under hybrid FPGA platforms and developed an open source controller called ZyCAP provide more efficient use of hardware resources in these architectures [38].

PR can bring quite a few benefits for designing FPGA hardware. Moreover, it enables a large implementation to be embedded on a small chip by increasing the effective logic density of the chip. When compared with full reconfiguration, PR has a distinct advantage of reduced reconfiguration time concerning the size of the configuration module, which corresponds to the chip area, which is to be reconfigured. Partial Reconfiguration architecture is suitable for adaptive hardware systems because of their easy adaptation to varying conditions when the data processing is done [39].

Partial Reconfiguration Design and Implementation

The two main techniques of PR are difference based and Module based [32]. The difference-based technique is achieved by creating a change to design and generate a bitstream from the variations of the designs. This method performs the switching of module configuration from one implementation to another quickly, since the differences between the bitstream are not significantly larger than the whole device bitstream. This technique shall not be followed, as the changes to the design are large, and the signal integrity is not assured on reconfigurable modules boundaries.

Fig. 6
figure 6

Xilinx Partial Reconfiguration Flow [1]

Full size image

Module-based design is a Xilinx Development System Option which works autonomously by merging into unique FPGA design from different modules [39]. The design of each module is at the top level design, which is considered as an independent module, and the parallel development permits modification of a module while the other modules are unaffected. Module-based PR involves in executing a series of procedures at the stage of design specification [40]. Then bit-stream is created individually for each reconfigurable module of the design. These reconfigurable modules have been represented in VHDL, and they are implemented on the FPGA board of Xilinx Virtex families with partial reconfiguration [41,42,43]. Xilinx PlanAhead Partial reconfiguration flow is shown in Fig. 6. Partial reconfiguration saves the silicon area, which enables multiple configurations to be interchanged and provide flexibility to replace the configuration. \(\hbox{Vivado}^{\textregistered }\) Design Suite software tools unlock the capability to reconfigure a section of a Xilinx FPGA device, whereas the remaining parts of the device remain functioning [44,45,46,47,48,49]. The \(\hbox{Vivado}^{\textregistered }\) Design Suite suggests a new approach for ultra-high productivity with next-generation IP-based and C/C++ design [50,51,52]. The design implementation of floor planning and I/O planning of Xilinx Zynq XC7Z020 using Vivado Design Suite is shown in Figs. 7 and 8, respectively.

Fig. 7
figure 7

Floor Planning of Xilinx Zynq XC7Z020 device and internal view of a slice

Full size image
Fig. 8
figure 8

I/O Planning of Xilinx Zynq XC7Z020 device

Full size image

Applications

The programming of RC systems can be done by directly program the logic gates inside the FPGA. Since FPGAs are free from instruction fetching operations, the instructions are built into the FPGA data path itself. FPGAs and their reconfigurability find their path in different applications such as data streaming, wireless communication systems, cryptography, network security, multimedia, DSP applications, medical research and therapy, bioinformatics, consumer electronics, automotive industries, military applications, artificial intelligence, deep learning and so on. Some of the applications benefited are listed in Table 4.

Cao Liang et al., represented an efficient architecture called SMARTCELL for data streaming applications using Altera Stratix II EP2S30 device benchmark platform [53]. This architecture showed better performance and low power consumption of about 52% than configurable FPGAs. Scott Hauck et al., explored the configuration compression and developed an algorithm to reduce the amount of data during reconfiguration in Xilinx XC6200 [54]. Usamah Algemili investigated the performance of the reconfigurable hardware FPGA for processing data streams using Moore’s voting algorithm and implemented on Xilinx \(\hbox{Zynq}^{\textregistered }\) board [55].

FPGA have gained quick acceptance over the past decades in wireless communication. Xue Liu et al., implemented FPGA-based reconfigurable down converter for wide band applications [56]. The proposed architecture was implemented in Xilinx FPGA XC7K70T-2FBG676 (Kintex-7 FPGA family) and Xilinx \(\hbox{Zynq}^{\textregistered }\). Jordane Lorandal et al., proposed FPGA implementation to evaluate performance and power comparison of wireless communication base band systems [57].

Xilinx \(\hbox{Zynq}^{\textregistered }\) SoC supports for the fields of wireless technology and its protocols. B.Drozdenko et al., analyzed a method for hardware and software co-designs for wireless transceivers using Xilinx Zynq-based reconfigurable platform [58]. C. Ebeling et al., developed an architecture called RaPiD—Reconfigurable Pipelined Datapath Architecture [59] in 1996. Later T.H.Pham et al., implemented an Orthogonal frequency-division multiplexing (OFDM) receiver in the reconfigurable architecture [60]. OFDM baseband design for FPGA-based cognitive radios with partial reconfiguration is proposed by them.

Being an integral part of embedded systems, FPGA provides security and mechanisms for privacy. Multiple cryptographic algorithms can be implemented on Xilinx Zynq 7000 series FPGA [61]. The implemented design showed high performance, better resource utilization and system flexibility. Huiyun Li et al., demonstrated an experiment of ionic attack into SRAM-based cryptographic integrated circuits [62]. The clustering of FPGA resources made an impact in cryptographic computing and implementing on Altera (DE2-115) development board [63].

FPGAs support the demands of hardware implementations in network protocol and provide intense security. A. Chattopadhyay et al., proposed a protocol to transmit videos from one place to other captured in real time and implemented on Xilinx Zynq XC7Z020 series [64]. FPGA implementations in network infrastructure security and other major issues in hardware techniques were discussed in [65]. [66] developed an efficient and secured wireless local area networks (WLANs) based on FPGA implementation for multimedia applications.

Mishra et al., developed a solution for FPGA-based reconfigurable systems and also presented Reconfiguration Over Network (ReON) protocol with the help of Xilinx Internal Configuration Access Port (ICAP) [67]. The integration of software-defined networking (SDN) and reconfigurable network platforms are described in [68].

FPGA hardware architectures deliver the capability of performing high-quality image and video processing applications by providing a trade-off between resource utilization and performance. Bin Zhang et al., presented a reconfigurable processor implemented on Intel Stratix II EP2S180 Series FPGA for binary image processing [69]. Mahmoud Meribout et al., suggested a non-invasive FPGA-based THz imaging system for multiphase flow measurement and imaging implemented on Altera Stratix V FPGA [70].

Digital Signal Processors lack the flexibility in their architectures which reduce the performance and increase the complexity, whereas FPGAs provide flexibility and parallelism. A. Lindoso et al., implemented fault tolerant LEON3 soft-core processor in Artix-7 FPGA [71]. Javier Hormigo et al., investigated and then experimented floating point implementation in FPGA for DSP applications [72]. Bajaj Ronak et al., demonstrated that the Xilinx FPGAs provide the multi-pumping flexibility in DSP blocks by reducing the resources [73]. Kentaro Sano and Satoru Yamamoto demonstrated the scalability of FPGAs using floating point DSP blocks and compared among FPGAs and GPUs [74].

FPGAs provide variety of applications in the field of medical research. Shadab Khan et al., developed an algorithm and implemented on the FPGA for Electrical impedance tomography (EIT) [75]. G. D. Licciardo et al., used Gabor filter for medical imaging applications implemented on Xilinx FPGA hardware [76]. For diagnostics, monitoring and therapeutic applications, Virtex FPGA and \(\hbox{Spartan}^{\textregistered }\) FPGA families could employ for satisfying a variety of processing and interfacing demands. The combinations of three-dimensional (3D) medical imaging and partial reconfiguration have been evolving in recent years. A. Ahmad et al., proposed two architectures based on transpose computation and partial reconfiguration and implemented three-dimensional (3D) Haar wavelet transform (HWT) on Xilinx Virtex-5 FPGAs [77].

Over the past few years, the demand for consumer electronics is increasing exponentially [78]. The recent trends in the consumer electronics market are in extreme uprising period in which FPGAs deserve a major role in the industry [79]. Some of the results have shown that PR could be handy in audio and video processing applications, such as MP3 decoding [80] and JPEG encoding [81]. [82] proposed a new architecture for content security encryption and decryption that is dynamically configured on Xilinx FPGA (XC2VP100).

FPGAs are capable of performing multi-threading operations which allow them to implement in various applications, including automotive industries. Modern vehicles incorporate hundreds of electronic control units which directly influence their power consumption and durability. Hence, reconfigurable hardware components come across their pathway in addressing these challenges and provide flexibility. Some of the researchers have demonstrated the development of PR in driver assistance systems [83]. The real-time video processing based on PR on FPGAs is presented [84], and Autovision architecture for driver assistance systems was developed by [85]. Shanker Shreejith et al., explained the necessity of reconfigurable computing in the automotive industries for the next generation [86].

FPGA computing has removed all the obstacles to make their way in bioinformatics. J.E. Duarte-Sánchez et al., designed a low-cost SoC-FPGA to process human genome and also implemented a hardware accelerator for multifractal analysis of DNA sequences [87]. G Chrysos et al., surveyed the applications and challenges of reconfigurable computing in the platform of bioinformatics [88]. [89] proposed a dynamic multi-classifier architecture of implementing dynamic partial reconfiguration combined with FPGAs that can be used in processing bioinformatics data .

[90] studied and explored the use of reconfiguration in military applications. FPGA will also find their use in space-based applications such as fault recovery and design of avionic equipment [91,92,93,94] proposed fine-grained dynamic reconfiguration method that could perform detection and recovering from configuration errors in SRAM FPGA-based Triple Modular Redundancy (TMR) devices for high radiation environment. Xilinx Microblaze TMR solution using Vivado Design Suite provides error detection and recovery for Xilinx devices [95]. PR has also been proposed in mitigating Single event upsets (SEUs) in SRAM-based FPGAs [96].

The need for technology improvements is more than before. With this acceleration, especially deep learning is yielding successful results along with FPGAs in the fields of object detection, voice recognition, medical analysis and so on. E.Wang et.al., [97] presented the first survey article for customized hardware accelerators and compared them with approximation for CNN and RNN (Recurrent Neural Networks). In [98], the authors have explained FPGA accelerators for convolution neural networks (CNNs) in order to increase the overall performance. Reconfigurable hardware accelerators can also be a different approach for implementing deep learning techniques. For object detection using CNN implemented on PYNQ board is presented [99]. In this study, Movidius USB-GPU is also experimented with PYNQ along with YOLO application is used for detecting various objects such as human, bicycle and a car. The experimental results in terms of calculation time and number of operations per image have shown that the performance of reconfigurable FPGA hardware is suitable for deep learning optimization.

Table 4 Constructive table for different Applications
Full size table

Recent Developments

AMAZON and Microsoft have launched FPGA cloud services [100]. The Asia-Pacific region seized the majority of market value in the global FPGA market and is expected to be the fastest increasing market during the estimated period. Growing applications in defense and aerospace, artificial intelligence, consumer electronics, deep learning and the automotive industry are a vital factor supporting their rapid growth in newer aspects and are presumed to steer the industries over the upcoming years. \(\hbox{Intel}^{\textregistered }\) introduced 10 nm technology based \(\hbox{Intel}^{\textregistered }\) \(\hbox{Agilent}^{\textregistered }\) FPGAs and SOCs to deliver high performance for applications such as data centers, networking, and edge computing [101]. Xilinx team up with Samsung to deploy world’s first 5G New Radio (NR) commercial deployment using the \(\hbox{Xilinx}^{\textregistered }\) UltraScale+ platform [102].

Summary

Reconfigurable computing has been progressed significantly over the years. A concise study of FPGA architectures has been carried out and analyzes the architectures of reconfigurable devices and their applications. This survey will pave the way for researchers to find suitable applications for FPGAs. Some of the potential application domains such as automotive, communication, aeronautical, defense, deep learning and consumer electronics provide well suited to support PR system design. Reconfigurable architectures have been developed from basic FPGA architecture to high-performance architectures. The major issue in coarse-grained reconfigurable architectures is its flexibility need to be addressed for reconfigurable processors in the future. Among the types of FPGAs, SRAM based are widely used because of their volatility and reprogrammability. Programming for reconfigurable architectures and complete virtualization of FPGA resources for PR are the challenging tasks. The simulation of floor planning and I/O planning of PR device like \(\hbox{Zynq}^{\textregistered }\) XC7Z020 is displayed with the help of \(\hbox{Vivado}^{\textregistered }\) Design Suite. The various applications of PR are explored with a wide range of domains. The reconfigurable computing will find its way in the fields of nanotechnology shortly.