1 Introduction

The miniaturization of CMOS devices is demanding, and the difficulty level for the investigation increases gradually with respect to physical size constraints, high power consumption, leakage current, expensive lithography costs, and the negative impact of short-channel effects [1]. Quantum dot cellular automata (QCA) and magnetic quantum dot cellular automata (MQCA) are two promising contenders for alternative computing paradigms to overcome these drawbacks. QCA technology requires low temperature for operation, whereas MQCA works at room temperature [2]. This new technology follows new approaches for both design and computation. In MQCA, quantum mechanical interaction is spin-based, and the nanomagnets work like tiny bar magnets. In nanomagnet-based designs, information is not transmitted from one place to another in electronic form. Instead, it is transmitted directly through magnetic attraction and repulsion, reversing the polarity of the north and south poles as they move from one magnet to another. This is almost equivalent to a NOT gate inverting the logic state slightly [3]. The nanomagnetic devices use two types of coupling, ferromagnetic and antiferromagnetic. With the help of this coupling concept, MQCA-based logic functionalities were verified after simulation studies [4,5,6]. A MQCA-based majority logic gate was first implemented by Imre et al. [7]. Subsequently, clocking structures and power analysis for nanomagnetic logic (NML) devices were shown by Niemier et al. [8]. After the demonstration of on-chip clocking, MQCA technology has become advantageous [9]. Alam et al. developed a CMOS-compatible clock and used it to evaluate all the NML constructs needed for a functionally complete logic set. They ensured that all possible input combinations to these constructs were considered during experiments. Furthermore, they designed the architecture to promote unidirectional data flow. Thus, NML is a promising contender for the latest computing paradigms as it consumes low power, and is non-volatile in nature. NML has the potential to operate at very high speed and has high integration density, making NML favorable for dense computing architectures. It is more reliable in high-radiation environments such as space exploration or certain medical applications.

To date, most of the researchers used the majority gate concept for the implementation of universal gates and basic gates. MQCA-based majority gates are investigated using driver magnets [7] and slant edge magnets [10] and they use ferromagnetic and antiferromagnetic wire architectures. Conventional majority gate designs relied on multiple nanomagnets and required significant area. In nanomagnet-based logic design, there has been a consistent emphasis on using a minimal number of nanomagnets, occupying the smallest area possible, and completing operations in the least amount of time [11]. With this in mind, we have introduced a groundbreaking area and energy-efficient comparator design using the non-majority logic gates as demonstrated in Fig. 1.

Fig. 1
figure 1

a Single-bit comparator schematic design using non-majority logic gates. Layout design of logic gates using three slant edge nanomagnets of varied lengths, b OR Layout A, c OR Layout B, d AND Layout A, e AND Layout B, f XOR Layout, g XNOR Layout, h single-bit comparator layout design with different clock zones (I, II, and III)

Full size image

The number of design layouts required to implement logic using NML devices may equal the number of logic variations. In contrast, traditional CMOS devices typically require only one design layout that can be reconfigured at run-time. However, the advantage of CMOS can be harnessed by successfully realizing on-chip clocking strategies [9] and programmable input devices [12, 13] will harness this advantage of CMOS. This paper presents a simulation demonstration of one of the NML strategies, i.e., MQCA with varied amplitude clock pulses and single-layout designs for the AND/OR gate and single-bit comparator, a first-of-its-kind strategy to the best of the authors’ knowledge.

The remainder of this paper is organized as follows. Related work is explained in Sect. 2, and the proposed methodology is presented in Sect. 3. Section 4 discusses the results, and Sect. 5 provides the conclusion.

2 Related work

This section overviews the logic gates and single-bit comparator designs proposed in the literature.

2.1 Majority gates and logic gates

The majority gate is the basic building block for combinational and sequential logic circuits. Most researchers used the concept of the majority gate to implement universal or basic logic gates [14]. The majority gate comprises three input nanomagnets that surround a central computational nanomagnet, as demonstrated by Imre et al. The authors presented the basic logic gate using the majority gate concept in the MQCA design [7]. The authors arrange the two orthogonal intersecting nanomagnetic lines such that the vertical line produces ferromagnetic coupling and the horizontal line produces antiferromagnetic coupling. With one of the inputs at a constant value of 1/0, the majority gate behaves as a NAND/NOR gate.

Afterward, Varga et al. demonstrated the functioning of logic gates with the help of the programmable input majority gate concept [12]. The authors used different sizes of input driver magnets, which occupy a large area. The coercivity of the nanomagnets increases as the length in the easy axis increases, i.e., large-aspect-ratio nanomagnets need a higher value of magnetic flux density to switch as shown in Fig. 2. We demonstrate the change in magnetization direction of a small nanomagnet (15 \(\times\) 20 \(\times\) 10 nm\(^{3}\)) at different magnetic flux densities.

Fig. 2
figure 2

Hysteresis curve for different aspect ratio nanomagnets

Full size image

Siddiq et al. reported logic gate structure for nanomagnets using the concept of electrically controlled inputs and slant edge output nanomagnets [15]. The authors demonstrated the on-chip clocking. They verified the results using simulation as well as experimental analysis. The experimental validation has been done using magnetic force microscopy. The limitation of this work is that bias field-driven inputs are a major concern for large circuits.

Li et al. proposed the majority gate structure using 45\(^\circ\) misalignment-free clocking mechanism [16]. The authors used the driver magnet structure and demonstrated with the help of a reversal clocking field which decreases in amplitude progressively. Afterward, they also implemented an adder with the help of inclined driver nanomagnets of different sizes [17]. The authors require additional circuitry to ensure proper timing, which increases the complexity of the majority gate structure.

Jaiswal et al. implemented a rotating majority gate (RMG) using slant-edge nanomagnets and ferromagnetic coupling concept among the nanomagnets [18]. The authors used different layouts and a single clock technique for RMG implementation. Subsequently, they also presented a full adder design using two RMGs and antiferromagnetic coupling between sum and carry outputs.

Motivated by the above research approaches, we implement first-of-its-kind area-efficient logic gates utilizing the varied-length slant edge nanomagnets shown in Fig. 3. OR layout designs A and B, AND layout designs A and B, XOR layout design, and XNOR layout design are demonstrated in Fig. 1b, c, d, e, f, and g, respectively.

Fig. 3
figure 3

a–d OR Layout A with varied external magnetic flux density, e–h AND Layout A with varied B\(_\textrm{ext}\)

Full size image

2.2 Comparator design

The comparator is the fundamental block of computing devices like ALU, CPU, etc. The function of the comparator is to compare the two logical values and give the output according to \(A<B\), \(A>B\), and \(A=B\). QCA-based comparator is demonstrated by [19,20,21] to utilize majority gate and XOR gate.

Bahar et al. demonstrated comparator design using majority gate and inverter logic only [22]. The authors demonstrated QCA architecture that works on the principle of multilayer crossing for fan-out, i.e., for accessing \(A=B\), the authors need extra crossover. They used one XOR gate, three inverter gates, and two majority gates, resulting in a large area overhead.

Majeed et al. implemented a QCA-based comparator using XNOR gates [19]. The authors need an extra cell to access the output cell. Subsequently, Khan et al. proposed the 1-bit magnitude comparator using single-layer or multilayer crossing networks [20]. The authors need 44 QCA cells, resulting in large area occupancy.

Sasamal et al. proposed big and scalable architecture for comparator design by reducing the number of crossovers [21]. They used two majority gates, two inverters, and one XOR gate. The advantage of the above design is that all input and output ports are easy to access on a single layer without using a multilayer structure.

Nanomagnetic logic-based comparator design demonstrated by Bhoi et al. They used the pNML technology and did the architectural design using the MagCAD tool [23]. They used six minority voters and one inverter in the layout design, which occupies a large bounding area of 2.4336 \(\upmu\)m\(^{2}\).

In this paper, we demonstrate a single-bit comparator design using the above-mentioned logic gates architecture in different clock zones. The schematic design of the single-bit comparator is shown in Fig. 1a. The layout design of the area-efficient single-bit comparator design is demonstrated in Fig. 4. Here we use three different clock zones and place the different logic gates, i.e., AND, OR, and XNOR gates, such as the coupling interaction between the different gates’ nanomagnets is negligible.

Fig. 4
figure 4

a Single-bit comparator layout design after \(B_H = -35 mT\) of applied magnetic flux density (B) for all clock zones (I, II and III), b \(B_L = 14 mT\) of applied B for I, \(B_M = 25 mT\) of applied B for II, III clock zones, c \(B_H\) of applied B for I and III clock zones, \(B_H\) followed by \(-B_M\) and then \(B_L\) for II clock zone, d \(-B_M\) of applied B for I clock zone, \(-B_L\) for III clock zone, \(B_H\) followed by \(-B_L\) for II clock zone

Full size image

3 Proposed methodology

In this study, we propose a novel approach to implement non-majority logic gates using programmable and varied-length slant edge nanomagnets along with different amplitude clock pulses. To showcase the applicability of proposed non-majority-based logic gates we demonstrated a single-bit comparator design using different clock zones.

3.1 Logic gates

In this section, we discuss novel non-majority logic gates based on MQCA. Our approach incorporates the concept of varied-length slant edge nanomagnets and utilizes different amplitude external magnetic flux densities (\(B_H, B_M, \& B_L\)) to create run-time reconfigurable non-majority logic gate architectures. As a result of the run-time reconfigurable structure, we achieve all the outputs corresponding to all input combinations using a single layout design. Programmable input logic circuits can implement multiple applications on a single chip and switch between functionalities when necessary due to their run-time reconfigurable nature. The proposed layouts of non-majority logic gates using distinct aspect ratio nanomagnets are shown in Fig. 1b–g. Here, the output nanomagnet is ferromagnetically coupled with the input nanomagnets. In Fig. 1b–g, the output nanomagnet is shown in red, and the input nanomagnets are in brown and orange.

We propose two layout designs for OR and AND gates by interchanging the position of large and small nanomagnets. We use varied external magnetic fields high field \(B_H = 35 mT\), medium field \(B_M = 25 mT\), and low field \(B_L = 14 mT\) to attain all output states corresponding to different input combinations using a single layout, as demonstrated in Fig. 3. We demonstrate the external magnetic flux density operation of OR layout A and AND layout A in Fig. 3. Likewise, we get the output for all the input combinations for OR layout B and AND layout B using the clock pulse, as shown in Fig. 3. We also define the following axioms A1 and A2 corresponding to the hysteresis curves, as shown in Fig. 2.

  1. A1:

    Increasing the aspect ratio of nanomagnets increases its coercivity along the easy axis.

  2. A2:

    A higher magnetic field is needed for the re-magnetization of large-size nanomagnets [12, 13, 24, 25].

According to axiom A1 and A2, nanomagnets \(\hbox {IN}_{{1}}\), \(\hbox {IN}_{{2}}\), and OP lengths are distinct. The varied magnetic flux density is needed to switch the nanomagnets from stable to null state for different aspect ratio nanomagnets. The minimum height of nanomagnets is 20 nm, and the geometric anisotopic ratio, i.e., height-to-width ratio, is 1.33, 1.6, and 2.67 for small, medium, and large nanomagnets. The width and thickness of all the nanomagnets are the same: 15 nm and 10 nm, respectively. This approach is similar to the conventional CMOS design, where a single layout design is used for different input combinations. The experimental validation of our proposed design is feasible as the on-chip clocking is discussed by Siddiq et al. [15] and Alam et al. [26].

3.2 Comparator design

To date, MQCA architectural design methodology works on the principle that different input combinations need a different layout for dipole-dipole coupling. This methodology could be a promising contender for fewer input bits. However, as the number of input bits increases, the number of layout designs also increases. To overcome this drawback, programmable input logic comes into the picture. To the best of the authors’ knowledge, we propose a single-bit comparator design for dipole-dipole coupling for the very first time. The output of the comparator is defined as:

$$\begin{aligned}{} & {} X(A<B)=A^{\prime } B \end{aligned}$$
(1)
$$\begin{aligned}{} & {} Y(A>B)=A B^{\prime } \end{aligned}$$
(2)
$$\begin{aligned}{} & {} Z(A=B)=A B+A^{\prime } B^{\prime } \end{aligned}$$
(3)

A and B are inputs, X, Y and Z are outputs for \(A<B, A>B\) and \(A=B\).

Fig. 5
figure 5

a–d Simulation result of the MQCA-based OR gate (Layout A) using MuMax3, a applied magnetic flux density (B) of −35 mT following a 0 mT, b 25 mT of applied B following a 0 mT, c 35 mT of applied B following a 0 mT, d −14 mT of applied B following a 0 mT; binary equivalent ‘1’ is represented by up arrow (green), binary equivalent ‘0’ by down arrow (blue) (Color figure online)

Full size image

The nanomagnetic design of the proposed single-bit comparator uses three different gates, as depicted in Fig. 1a. The proposed architecture along with varied external magnetic flux densities is depicted in Fig. 4. Here we use two AND gate layouts and one XNOR gate layout in different clock zones. We utilize variable amplitude clock pulses for different clock zones, which makes the proposed comparator layout an area-efficient design [27, 28]. The size of input nanomagnets ‘A’ and ‘B’ is 15 \(\times\) 40 \(\times\) 10 nm\(^{3}\) and 15 \(\times\) 20 \(\times\) 10 nm\(^{3}\), respectively. We choose the output nanomagnet size to be 15 \(\times\) 24 \(\times\) 10 nm\(^{3}\). Under the influence of high magnetic flux density (\(B_H = 35 mT\)), all the nanomagnets are forced to a null state. When we apply medium magnetic flux density (\(B_M = 25 mT\)), medium and least-sized nanomagnets change their states. For the remaining input combinations, we apply low magnetic flux density (\(B_L = 14 mT\)) then there will be a change in least-sized nanomagnets only. We get the exact output for all the input combinations using this approach. All the layout architectures have been done in MuMax3, and their simulation results will be discussed in Sect. 4.

Fig. 6
figure 6

a–d Simulation result of the MQCA-based OR gate (Layout B) using MuMax3, a applied magnetic flux density (B) of −35 mT following a 0 mT, b 25 mT of applied B following a 0 mT, c 35 mT of applied B following a 0 mT, d −14 mT of applied B following a 0 mT; binary equivalent ‘1’ is represented by up arrow (green), binary equivalent ‘0’ by down arrow (blue) (Color figure online)

Full size image

4 Simulation results and discussion

We have utilized GPU accelerated MuMax3 [29] to implement the proposed designs to provide proof of concept. The DyNaMat group at Ghent University developed and maintains the MuMax3 simulation platform, which gives approximately 100 times faster performance than OOMMF, a CPU-based simulation platform. The Landau-Lifshitz-Gilbert (LLG) equation is solved using the 4\(^\textrm{th}\)-order Runge-Kutta (RK45) evolver as a time step control. To achieve adaptive time step control, the Dormand-Prince method is utilized, which offers 5\(^\textrm{th}\)-order convergence and 4\(^\textrm{th}\)-order error estimation. While most micromagnetic simulations have historically been run on OOMMF, utilizing a GPU-accelerated micromagnetic simulator enables smaller tasks to be run in parallel, resulting in faster simulations. Figs. 5 and 6 show the results of the micromagnetic simulations for design layouts A and B of the proposed OR gate. The proposed AND layouts A and B are demonstrated in Figs. 7 and 8. The XOR and XNOR layout design, shown in Fig. 1f, g, and their simulation results are presented in Figs. 9 and 10. Figure 11 illustrates the micromagnetic simulation results of the proposed comparator designs depicted in Fig. 4.

The appropriate aspect ratio of nanomagnets is crucial in MQCA circuits. If the ratio is too high, the nanomagnets may become unstable and cause the circuit to malfunction. On the other hand, if the ratio is too low, it may lead to incorrect data propagation due to the high instability of the nanomagnets along their hard axis. To determine the optimal aspect ratio, multiple simulations were performed in MuMax3 as Jaiswal et al. have done [30]. In the proposed MQCA circuits, the large, medium, and small nanomagnets have differences in length only. Width and thickness are the same for the logic gates and comparator layout architectures.

Fig. 7
figure 7

a–d Simulation result of the MQCA-based AND gate (Layout A) using MuMax3, a applied magnetic flux density (B) of 35 mT following a 0 mT, b −25 mT of applied B following a 0 mT, c −35 mT of applied B following a 0 mT, d 14 mT of applied B following a 0 mT; binary equivalent ‘1’ is represented by up arrow (green), binary equivalent ‘0’ by down arrow (blue) (Color figure online)

Full size image
Fig. 8
figure 8

a–d Simulation result of the MQCA-based AND gate (Layout B) using MuMax3, a applied magnetic flux density (B) of 35 mT following a 0 mT, b −25 mT of applied B following a 0 mT, c −35 mT of applied B following a 0 mT, d 14 mT of applied B following a 0 mT; binary equivalent ‘1’ is represented by up arrow (green), binary equivalent ‘0’ by down arrow (blue) (Color figure online)

Full size image
Fig. 9
figure 9

a–d Simulation result of the MQCA-based XOR gate using MuMax3, a applied magnetic flux density (B) of −35 mT following a 0 mT, b 25 mT of applied B following a 0 mT, c 35 mT of applied B following a 0 mT, afterward −14mT of applied B following a 0 mT d −25 mT of applied B following a 0 mT, afterward 14 mT of applied B following a 0 mT; binary equivalent ‘1’ is represented by up arrow (green), binary equivalent ‘0’ by down arrow (blue) (Color figure online)

Full size image
Fig. 10
figure 10

a–d Simulation result of the MQCA-based XNOR gate using MuMax3, a applied magnetic flux density (B) of −35 mT following a 0 mT, b 25 mT of applied B following a 0 mT, c 35 mT of applied B following a 0 mT, afterward −14mT of applied B following a 0 mT d −25 mT of applied B following a 0 mT, afterward 14 mT of applied B following a 0 mT; binary equivalent ‘1’ is represented by up arrow (green), binary equivalent ‘0’ by down arrow (blue) (Color figure online)

Full size image

The simulations were conducted using a saturation magnetization of 8 \(\times\) 10\(^{5}\) A/m, an exchange stiffness constant of 1.3 \(\times\) 10\(^{-13}\) J/m, and a damping coefficient of 0.25. Permalloy was the material of choice, consisting of a poly-crystalline structure with a composition of 21.5% iron, and 78.5% nickel. It lacked a uniaxial anisotropy constant [31]. The remarkable exchange energy of permalloy makes it a preferred choice for a soft ferromagnetic material, surpassing magneto-crystalline anisotropy. The absence of a uniaxial anisotropy constant in Permalloy indicates that the magnetic anisotropy aligns easily with the long axis of the material, dependent solely on the shape of the nanomagnets.

Figures 5 and 6 demonstrates OR layouts A and B simulation results, where all the input combinations are verified using the graphical plot of applied external magnetic flux density and the magnetization direction of input and output nanomagnets w.r.t time in seconds. Likewise AND layout A and B is verified which is demonstrated in Figs. 7 and 8. XOR layout design’s simulation results are shown in Fig. 9. Here for input combinations ‘10’ and ‘11’, we get the simulation results after the application of one clock pulse only while for ‘00’ and ‘01’ we have to apply two clock pulses simultaneously. Likewise, we get MuMax3 simulation output of XNOR layout for all input combinations which is illustrated in Fig. 10.

Fig. 11
figure 11

MuMax3 simulation result of single-bit comparator design a after \(B_H = -35 mT\) of applied magnetic flux density (B) for all clock zones (I, II and III), b \(B_L = 14 mT\) of applied B for I, \(B_M = 25 mT\) of applied B for II, III clock zones, c \(B_H\) of applied B for I and III clock zones, \(B_H\) followed by \(-B_M\) and then \(B_L\) for II clock zone, d \(-B_M\) of applied B for I clock zone, \(-B_L\) for III clock zone, \(B_H\) followed by \(-B_L\) for II clock zone, binary equivalent ‘1’ is represented by up arrow (green), binary equivalent ‘0’ by down arrow (blue), e–h real-time MFM images of the simulation outputs for 10, 11, 01, and 00 input combinations, respectively

Full size image

The single-bit comparator design’s simulation results in remanent magnetization form are demonstrated in Fig. 11a–d. For input combination ‘10’ output X = 0 \((A<B)\), Z = 0 \((A=B)\) and Y = 1 \((A>B)\) which is illustrated in Fig. 11a. For input combination ‘11’ and ‘00’ output X = 0 \((A<B)\), Z = 1 \((A=B)\) and Y = 0 \((A>B)\) shown in Fig. 11b, d. Input combination ‘01’ output X = 1 \((A<B)\), Z = 0 \((A=B)\) and Y = 0 \((A>B)\) is illustrated in Fig. 11c. The bit value ‘1’ can be determined by upward direction magnetization, and the nanomagnets are shown in green, while the bit value ‘0’ by downward magnetization and nanomagnets are shown in blue. Real-time magnetic force microscope (MFM) images of the simulation outputs for 10, 11, 01, and 10 are shown in Fig. 11e–h. The binary value for the nanomagnets can be determined with the help of the contrast. Solid dark black contrast shows the magnetization direction of the nanomagnets pointing towards the probe. Bright white contrast shows the magnetization pointing away from the probe. Our simulation study reported here focuses on the sub-50-nm design, motivated by the experimental confirmation of the potential fabrication of our proposed design methodology, as discussed by Gavagnin et al. [32]. This confirmation encourages further exploration and analysis of the design through simulations. By investigating the performance and characteristics of the sub-50-nm design, we aim to gain valuable insights and assess its viability for practical implementation.

The kink energy for a nanomagnet is typically defined as the difference between the energy of the meta-stable (frustrated) state and the energy of the desired ground state, as expressed in Eq. 4. This energy difference is commonly referred to as the kink energy, denoted as \(E_{Kink}\), and is given by:

$$\begin{aligned} E_{Kink}=U_{MS}-U_G \end{aligned}$$
(4)

Here, \(U_{MS}\) represents the energy associated with the meta-stable state of the nanomagnet, while \(U_G\) represents the energy associated with the desired ground state. By subtracting the energy of the ground state from that of the meta-stable state, we obtain the energy required to transition from the meta-stable to the ground state, which is the kink energy [33]. After applying 35 mT external magnetic flux density, the kink energy is 8.93 \(\times\) 10\(^{-21}\) J, whereas kink energy for 25 mT and 14 mT is much less, 2.25 \(\times\) 10\(^{-21}\) J and 1.63 \(\times\) 10\(^{-21}\) J, respectively.

Fig. 12
figure 12

Temperature analysis for 15 \(\times\) 40 \(\times\) 10 nm\(^{3}\) slant edge nanomagnet at 0, 5, 50, and 60K

Full size image

The total energy, exchange energy, and demagnetization energy are illustrated in Table 1 for AND and OR layout A and B. When the system is in the ground state, i.e., zero external magnetic flux density after the application of varied magnetic flux densities, demagnetization and total energies are nearly equal and exchange energy is much lower than the total and demagnetization energy. By default, the MuMax3-based fourth-order Runge-Kutta (RK45) evolver performs micromagnetic simulation at 0K. We have done the simulation for 15 \(\times\) 40 \(\times\) 10 nm\(^{3}\) slant edge nanomagnets at different temperatures, i.e., 0K, 5K, 50K, 60K, 100K, 273K, and 300K, and analyzed the change in switching field and coupling energies. The total energy increases with the temperature while the exchange and demagnetization energies remain the same. The switching field, i.e., external magnetic flux density decreases as we increase the temperature as shown in Fig. 12. As we used sub-50-nm nanomagnets, magnetic polarization changes from a stable state to a meta-stable state after the application of 2 mT magnetic flux density at 60K temperature, and there is a misalignment in magnetization while increasing temperature above 70K. In this study, our focus is on implementing an area-efficient comparator design and its micromagnetic simulation analysis. In future works, we expect to remove the temperature dependency of sub-50-nm nanomagnets using the interlayer exchange coupled (IEC) approach as suggested by Mattela et al. [34].

Table 1 Different energies associated with AND layout and OR layout designs
Full size table

Table 2 illustrates the performance comparison of the proposed MQCA-based run-time reconfigurable (RR) comparator design with the existing design in terms of the number of nanomagnets, area occupancy, and area usage. Our proposed design exhibits \(\sim\)56%-67% reduction in area occupancy compared to the QCA designs and \(\sim\)99% reduction compared to the existing MQCA design. The number of nanodots decreases by \(\sim\)50%-80% in comparison to the existing comparator design. The delay in the single-bit comparator for one input combination is 1 ns and the total delay is 7 ns for verification of all the input combinations.

Table 2 Comparison of the proposed MQCA-based run-time reconfigurable (RR) comparator design with state of art designs utilizing different design metrics
Full size table

5 Conclusion

In this research study, the authors proposed new designs for area-efficient nanomagnetic-based non-majority logic gates. To showcase the scalability of the proposed design a single-bit comparator design was introduced. It uses three logic gates and consists of only nine nanomagnets, resulting in a significant reduction in the number of nanomagnets required compared to the current state-of-the-art. Our design exhibits 99% area reduction and 50% reduction in the number of nanomagnets compared to the existing MQCA design. The authors aim to create nanomagnetic computing element libraries for computer-aided design tools to develop the proposed design further. The authors highlight the potential for future exploration of building higher-bit comparator designs. Further extensions such as an interlayer-exchange-coupled approach, placement automation using A*, and genetic algorithm could be investigated.