1 Introduction

As per Moore’s law, the size of devices is diminishing such that twice as many transistors can be fit onto a single chip every 18 months. However, complementary metal–oxide–semiconductor (CMOS) reaches its technological and economic limits beyond a certain degree of scaling, facing various limitations, e.g., in terms of physical dimensions, power consumption, leakage current, higher lithography costs, and short-channel effects [1]. Researchers have thus introduced a new configuration in which information processing is based on magnetism, where interacting submicron magnets are used to perform the logic operations and propagate information at room temperature [2]. This method is known as nanomagnetic logic (NML). This technology does not require transistors to perform the magnetic operations at the nanoscale. Nanomagnetic elements encode the logical information in the magnetization direction and transmit this information to neighboring magnets through their dipole field coupling. The main advantages of nanomagnets are their scalability, the nonvolatility of the stored information, their immunity to radiation, the lack of leakage currents, and their very low power consumption [3]. The number of wires in the circuit is thereby reduced, overcoming signal routing challenges. Nanomagnets can be easily fabricated at room temperature [4]. Nanomagnetic logic allows the integration of memory and digital logic circuits into a single system formed of various layers. Nanomagnetic logic can be divided into two types based on the orientation of the magnetic field: in-plane nonmagnetic logic (iNML) and perpendicular nanomagnetic logic (pNML), when the orientation is in-plane or perpendicular to the plane, respectively. iNML suffers from a few disadvantages such as limited cascaded elements, due to which more than one clock pulse is required. pNML technology is preferred due to its intrinsic physical properties, and because only a single clock pulse is required for the system [5], making such circuits more compact and simpler in design. Domain wall conductors are adopted for signal routing in monolithic 3D circuits [6]. To ensure reliable pNML computations, time-dependent nucleation in field-based coupled nanomagnets was demonstrated in Ref. [7]. In pNML technology, the domain nucleation field can be tuned by using perpendicular magnetic anisotropy and a 60% reduction in the switching field is observed when the ends of a wire are designed to have triangular points as compared with a rectangular shaped [8]. pNML technology is appropriate for the realization of threshold logic gates (TLGs). A TLG-based full adder (FA) architecture based on a new five-input majority-voter (MV) gate was demonstrated in Ref. [9]. Different digital circuits such as 4 × 4 memory [10], one-bit FA designs [11,12,13], combinational circuits such as comparators, decoders, and multiplexers [14,15,16], and half-subtractors and code converters [17] are described in state-of-the art work. An adder design was adequately addressed in Ref. [18], relying on a robust, low-energy-dissipation scheme that introduces regular clock zones in quantum-dot cellular automata (QCA) technology. Exploring digital circuits based on nanomagnetic logic, a flexible electronic design automation (EDA) framework known as ToPolinano is used to simulate and test different 3D digital circuits in ref. [19]. Digital circuits using QCA technology for combinational and sequential circuits such as even-parity generators [20], and multiplexer and demultiplexer circuits were implemented in Refs. [21, 22]. New parity generators, parity checkers, multiplexers, and ALUs were thus synthesized for the first time using pNML technology as per our literature review.

In this paper, the 3D pNML implementation of different digital circuits with, e.g., Ex-OR gate, parity generator (PG), parity checker (PC) circuits, 2-to-1 multiplexer, 4-to-1 multiplexer, and ALU functionality are presented. The various digital circuits are synthesized by using pNML logic. Experimental outcomes when using various types of magnet reveal that the newly designed digital circuit architectures based on nanomagnetic logic achieve improved delay, area, and magnet count with negligible hardware overhead. Finally, detailed simulations using the default settings for pNML technology are performed to confirm the correct functionality of the new designs of the various digital circuits. PG and PC circuits are used in the error detection and error correction method. Multiplexing (mux) plays an essential role in selecting any one of the input signals from several incoming input signals by using the data from the select line and passing it onto the output line. The ALU is used to perform arithmetic and logic operation in a central processing units (CPU). The circuit is designed in MagCAD, a custom layout editor tool. The MagCAD 2.10.0 tool is implemented in C++ but is also available in other language platforms [19]. Once the design phase is completed, MagCAD automatically generates the timing parameters as well as a Verilog net list and technology definition. MagCAD automatically generates and exports the Verilog code for the circuit. In the extracted net list, all the components in the layout are interpreted as different elements in net-list form. By using simulators such as Xilinx Vivado Design Suite 2020.1.1, simulation results can be obtained. Furthermore, we calculate parameters such as the bounding box area and latency. The newly designed digital circuits can be utilized as better choices for the synthesis of complex control units for processor designs. The major pillars of the proposed work are as follows:

  • Compact designs with PG, PC, multiplexer, and ALU functionality based on pNML technology are investigated.

  • The proposed design for the 2:1 multiplexer is equally valid for higher-order (4:1) multiplexer designs according to the evaluation of the minimal bounded area.

  • The estimate latency of the circuits with, e.g., PG, PC, multiplexer, and ALU functionality, is evaluated for different input combinations.

  • The bounding box area of the proposed ALU is 58.59 µm2 as evaluated based on the custom layout design in pNML technology.

  • The simulation results for the proposed designs with, e.g., PG, PC, multiplexer, and ALU functionality, are as accurate as for QCA- and CMOS-based designs.

  • The cost-efficiency is evaluated based on a comparison of existing with the proposed designs.

The remainder of this manuscript is organized as follows: An introduction and the state of the art of research on mux, PG, PC, and ALU circuits are presented in this Sect. 1. Section 2 presents a background study on NML structures and the minority-voter gate. The synthesis, layout, and outcomes of the newly proposed PG, PC, mux, and ALU and a comparison of their results are presented in Sect. 3. Furthermore, Sect. 3 deals with the 3D architecture of the ALU using the proposed multiplexer. A comparison with state-of-the-art work is presented in Sect. 3, and finally conclusions are presented in Sect. 4.

2 Basic terminology related to pNML

In this section, the basic terminology of nanomagnetic logic is discussed. Because this article uses various types of magnet, they are discussed in advance for readability. The basic building blocks of pNML technology are the minority voter and inverter. Here, we illustrate some elements of pNML technology used in this article.

Figure 1a presents the pNML layout of an inverter. An inverter is used to invert the input signal and to split critical paths. In the inverter layout, the input-type magnet is connected to the output-type magnet. The output-type magnet is known as an artificial nucleation center (ANC), as shown in Fig. 1b. In pNML, point-to-point connection is enabled by magnet wires known as “domain wall” magnets, as shown in Fig. 1c. Figure 1d shows a corner magnet, which is used to produce an output with 90° rotation. Figure 1e shows a “via magnet,” which is used to connect to a nucleation center placed on an adjacent plane. To split the input into two different directions, the “T-shaped” magnet shown in Fig. 1f is used. The “X-shaped” magnet is used to split an input into three different directions, as shown in Fig. 1g. To terminate a magnetic wire, a “pad magnet” is used, as depicted in Fig. 1h. Pads are used as nucleation centers for the output. To create a particular logic gate, a fixed “0” and fixed “1” input are required, as depicted in Fig. 1i and j, respectively.

Fig. 1
figure 1

The elements of pNML: (a) an inverter magnet, (b) an artificial nucleation center, (c) a domain wall magnet, (d) a corner magnet, (e) a via magnet, (f) a T-shaped magnet, (g) an X-connection magnet, (h) a pad magnet, (i) a fixed “0”, and (j) a fixed “1”

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2.1 The architecture of a minority voter gate

In the minority voter (mv) gate, the inputs are connected through a nucleation center, while the output (Y) is connected to a pad magnet. The output will take the minimum value of the logic values of A, B, and C. The pNML schematic of mv gate is shown in Fig. 2a. The inputs A and B and the output (Y) lie in the same layer, whereas the input C is on a different layer in the layout of the mv gate. The two different layers are included to achieve proper magnetization between the magnets, which is three dimensional in nature, as shown in Fig. 2b. In an mv gate, when the input A is fixed at “0”, the mv gate acts as a NAND gate, while when input A is fixed at “1”, it acts as a NOR gate. The corresponding truth table of the mv gate is depicted in Table 1. The ANC constitutes an mv gate with an odd number of inputs, i.e. a minimum of one and a maximum of five inputs [19]. The nucleation center is influenced by the superposition of the coupling of the odd inputs, while the outputs depend on the clock signal and inputs.

Fig. 2
figure 2

The schematic and layout of the minority voter gate

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Table 1 The truth table of the minority voter gate
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3 The proposed digital circuit models

In this section, we design the digital circuits using nanomagnetic logic based on pNML technology. The custom layout of the proposed circuits such as PG, PC, mux, and ALU is drawn using the layout editor tool MagCAD 2.10.0. The functionality of each circuit is verified to confirm its correct operation according to the desired Boolean expression. In the custom layout editor, we use pNML technology to synthesize all the layout designs. All the inputs to the custom layout are applied using nucleation centers.

3.1 The newly proposed Ex-OR gate

An exclusive-or (Ex-OR) gate performs an XOR operation on its digital inputs. For an Ex-OR gate, if the number of inputs with value of “1” is odd, it produces a true (high or 1) output, whereas otherwise it produces a false (low or 0) output. For a two-input Ex-OR gate, the output will be “1” if both the inputs are different but “0” if they are the same. Figure 3a shows a schematic of the Ex-OR gate. The mv-gate-based Ex-OR is modeled by Eq. 1. The inputs (A and B) are initialized as layer 0 type; the input signals to mv1 are B, 1, and the inverse of A, while the inputs to mv2 are A, 1, and the inverse of B. The output of mv1 and mv2 is applied as an input to mv3, along with one fixed input of 1, as shown in Fig. 3b. The pNML layout always gives the inverted output. The Ex-OR layout uses a total of three mv gates, as depicted in Fig. 3c. The bounding box area of the proposed model is 8.01 µm2. The simulation results for this 3D pNML layout of the Ex-OR gate are shown in Fig. 4. The computation table for four different combinations along with the latency results are evaluated and summarized in Table 2.

$$ \begin{aligned} {\mathrm{Where}}\;C & = \overline{{M_{3} \left( {1,M_{1} \left( {1,\overline{A} ,B} \right),M_{2} \left( {1,A,\overline{B} } \right)} \right)}} \\ & = \overline{{M_{3} \left( {1,\overline{{\overline{A} + B}} ,\overline{{A + \overline{B} }} } \right)}} \\ & = \overline{{M_{3} \left( {1,A\overline{B} ,\overline{A} B} \right)}} \\ & = \overline{\overline{{A\overline{B} + \overline{A} B}}} = = A\overline{B} + \overline{A} B \\ \end{aligned} $$
(1)
Fig. 3
figure 3

The proposed Ex-OR gate: (a) a schematic, (b) the pNML block diagram, and (c) the pNML architecture

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Fig. 4
figure 4

The simulation results for the Ex-OR gate using nanomagnetic logic based on pNML

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Table 2 The computational table for the Ex-OR gate
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3.2 The newly proposed even-parity generator circuit in pNML technology

The parity generator (PG) circuit is a type of combinational circuit used to generate the parity bit, a popular technique to detect errors during data transmission. The parity bit is added to the transmitted data stream for error control. If a parity bit of “0” is added to the data stream (known as an even-parity generator), it indicates that there are an even number of “1” values in the transmitted data stream. If a parity bit of “1” is added to the data stream (known as an odd-parity generator), it indicates that there is an odd number of “1” values present in the transmitted data stream. The schematic of the PG is shown in Fig. 5a. Figure 5b depicts the pNML block diagram of the PG. The proposed PG uses two Ex-OR gates. All the inputs are initialized with layer 0, as shown in Fig. 5c. the PG performs the modulo 2 operation between the three inputs, i.e., A, B, and C. The output of the first Ex-OR gate is fed to the second Ex-OR gate. The proposed PG uses a total six of mv gates, as shown in Fig. 5b. The output Y is inverted to obtain the required result. The bounding box area of the proposed custom layout of the PG is 21.06 um2 when based on pNML technology, as depicted in Fig. 5c. The simulation results for the 3D pNML custom layout of the PG circuit are shown in Fig. 6. The PG output based on the modeling Eq. 2 is shown. The computational table based on different input combinations to the PG is evaluated and presented in Table 3.

$$ \begin{aligned} {\mathrm{Where}},\;x & = M_{3} \left( {1,M_{1} \left( {1,\overline{A} ,B} \right),M_{2} \left( {1,A,\overline{B} } \right)} \right) \\ & = \overline{{M_{3} \left( {1,\overline{{\overline{A} + B}} ,\overline{{A + \overline{B} }} } \right)}} \\ & = \overline{{M_{3} \left( {1,A\overline{B} ,\overline{A} B} \right)}} \\ & = \overline{\overline{{A\overline{B} + \overline{A} B}}} \\ & = A\overline{B} + \overline{A} B = A \oplus B \\ Y & = \overline{{M_{6} \left( {1,M_{4} \left( {1,\overline{X} ,C} \right),M_{5} \left( {1,\overline{C} ,X} \right)} \right)}} \\ & = \overline{{M_{6} \left( {1,\overline{{\overline{X} + C}} ,\overline{{\overline{C} + X}} } \right)}} = \overline{{M_{6} \left( {1,X\overline{C} ,\overline{X} C} \right)}} \\ & = \overline{\overline{{X\overline{C} + \overline{X} C}}} = X\overline{C} + \overline{X} C = A \oplus B \oplus C \\ \end{aligned} $$
(2)
Fig. 5
figure 5

The proposed PG circuit: (a) a schematic, (b) the pNML block diagram, and (c) the pNML architecture

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Fig. 6
figure 6

The simulation results for the PG using nanomagnetic pNML

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Table 3 The computational table of the PG circuit with latency analysis
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3.3 The proposed even-parity checker circuit in pNML technology

A parity checker (PC) is used to detect errors in data transmission at the receiver end. The block diagram of the PC is shown in Fig. 7a. At the receiver end, the number of “1” values in the transmitted data stream along with the parity is counted. If the number of “1” values matches the transmitted parity bit, it means that there is no error in the received data. The outputs of the first and second Ex-OR gates are fed to the third Ex-OR gate, and the final output is taken from the third Ex-OR gate, as depicted in Fig. 7b. All the inputs (A, B, C, and P) are initialized with layer 0, as shown in Fig. 7c. The custom layout based on pNML technology for the PC circuit uses a total of nine mv gates. The bounding box area of the proposed model is 29.07 um2. The simulation results for the 3D pNML circuit for the PC are shown in Fig. 8. The model equations used to synthesize the PC outputs based on the mv gates are evaluated by using Eqs. 3, 4, and 5. To evaluate the latency of the proposed PC, four combinations of inputs are taken and the simulation performed. The computation table for the PC is presented in Table 4.

$$ \begin{aligned} {\mathrm{Intermediate}}\;{\mathrm{output}}\;1\;X & = \overline{{M_{3} \left( {1,M_{1} \left( {1,\overline{A} ,B} \right),M_{2} \left( {1,A,\overline{B} } \right)} \right)}} \\ & = \overline{{M_{3} \left( {1,\overline{{\overline{A} + B}} ,\overline{{A + \overline{B} }} } \right)}} \\ & = \overline{{M_{3} \left( {1,A\overline{B} ,\overline{A} B} \right)}} \\ & = \overline{\overline{{A\overline{B} + \overline{A} B}}} = A\overline{B} + \overline{A} B = A \oplus B \\ \end{aligned} $$
(3)
$$ \begin{aligned} {\mathrm{Intermediate}}\;{\mathrm{output}}\;2\;Z & = \overline{{M_{6} \left( {1,M_{4} \left( {1,\overline{C} ,P} \right),M_{5} \left( {1,C,\overline{P} } \right)} \right)}} \\ & = \overline{{M_{6} \left( {1,\overline{{\overline{C} + P}} ,\overline{{C + \overline{P} }} } \right)}} \\ & = \overline{{M_{6} \left( {1,C\overline{P} ,\overline{C} P} \right)}} \\ & = C\overline{P} + \overline{C} P = C \oplus P \\ & = \overline{\overline{{C\overline{P} + \overline{C} P}}} \\ \end{aligned} $$
(4)
$$ \begin{aligned} {\mathrm{Final}}\;{\mathrm{output}}\;Y & = \overline{{M_{9} \left( {1,M_{7} \left( {1,Z,\overline{X} } \right),M_{8} \left( {1,X,\overline{Z} } \right)} \right)}} \\ & = \overline{{M_{9} \left( {1,\overline{{Z + \overline{X} }} ,\overline{{X + \overline{Z} }} } \right)}} \\ & = \overline{{M_{9} \left( {1,\overline{Z} X,Z\overline{X} } \right)}} \\ & = \overline{\overline{{\overline{Z} X + Z\overline{X} }}} = \overline{Z} X + Z\overline{X} = A \oplus B \oplus C \oplus P, \\ \end{aligned} $$
(5)
Fig. 7
figure 7

The proposed PC circuit: (a) the block diagram, (b) the pNML schematic, and (c) the pNML layout

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Fig. 8
figure 8

The simulation results for the PC using nanomagnetic pNML

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Table 4 The computational table for the PC circuit
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3.4 Comparative results of the parity generator and parity checker circuits

The results for the newly proposed and previous PG and PC circuits are presented in this section. The results presented in Table 5 show that the newly proposed pNML-based PG and PC are superior to the previous PG and PC designs in terms of area, delay (latency), and number of layers, clocks, cells, or magnets. The comparative results indicate that the new PG and PC are superior compared with available designs in literature [20, 23,24,25,26,27,28,29,30]. A complete assessment of the new and previous PG and PC designs is presented in Table 5. The new design for the PG achieves an improvement of 65.85%, 48.14%, and 71.42% in terms of the number of magnets or cells and the number of layers or clock counts, respectively, in comparison with Refs. [28,29,30]. Compared with the reference PC design reported in [28, 30], the new design described herein offers an improvement of 66.66%, 27.77%, 77.77%, and 71.42% in the number of magnets or cells and the number of layers or clock counts, respectively. The new design for the PG and PC in pNML technology requires fewer magnets and layers and achieves shorter latency. Furthermore, the proposed PG and PC designs are based on multilayer pNML technology. These low cost designs for PG and PC circuits expand the application possibilities for complex, high density, and fast computing speed nanocircuits.

Table 5 A comparison of the parameters of the parity generator and checker circuits
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3.5 The proposed multiplexer in pNML technology

A multiplexer (also known as a data selector) has 2n input lines as well as n select lines. A 2-to-1 mux has two inputs (A, B) and one select line (SEL), as shown in Fig. 9a. The SEL is used to select any one of the inputs to be passed to the output line. Here, all the inputs A, B, and SEL are initialized with a layer “0”; the input to the first mv1 is A, the invoice of SEL, and fixed “0”. The input to mv2 is B, SEL, and fixed “0”. The output of both mv gates is fed to mv3, which produces the desired output, as illustrated in Fig. 9b. The bounding box area of the proposed model is 13.5 µm2. The new mux uses two layers (layer 0 and layer 1) based on magnets. The designed layout of the 2:1 mux in pNML technology is depicted in Fig. 9c. The simulation results are shown in Fig. 10. If the input SEL combination is 0, the accurate output combination of Y = A is found, as shown in Fig. 10. The output for a 2:1 mux is computed from Eq. 6, where A, B and SEL are the inputs and Y is the output. The latency for the proposed 2:1 mux designed in pNML technology is presented in Table 6.

$$ \begin{aligned} {\mathrm{Output}}\;Y & = M_{3} \left( {0,M_{1} \left( {0,A,\overline{SEL} } \right),M_{2} \left( {0,SEL,B} \right)} \right) \\ & = M3\left( {0,\overline{{A \cdot \overline{SEL} }} ,\overline{B \cdot SEL} } \right) \\ & = \overline{{\overline{{A.\overline{SEL} }} \cdot \overline{B \cdot SEL} }} \\ & = \overline{{\overline{{A.\overline{SEL} }} }} + \overline{\overline{B \cdot SEL}} \\ & = A.\overline{SEL} + B \cdot SEL \\ \end{aligned} $$
(6)
Fig. 9
figure 9

The proposed 2:1 mux circuit: (a) the block diagram, (b) the pNML ,schematic, and (c) the pNML layout

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Fig. 10
figure 10

The simulation results for the 2:1 mux using nanomagnetic pNML

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Table 6 The computational table of the 2-to-1 multiplexer
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3.6 The proposed architecture of the 4-to-1 multiplexer

A 4-to-1 mux consists of two 2-to-1 mux circuits. It has four input lines (a, b, c, and d) and two select lines (s0 and s1), as shown in Fig. 11a. The truth table for the 4-to-1 mux is presented in Table 7, where s0 and s1 are the select lines, a, b, c, and d are the input lines, and y is the output line. To obtain the desired output of the 4-to-1 mux, the inputs a, b, and c, and s0 and s1, are initialized with a layer “0”, whereas input d is initialized with layer “1”. Here, the inverted input is applied in all the cases to get the multiplexer output equation. The schematic based on the mv and inverter of the new 4:1 mux is presented in Fig. 11b, and the layout of the pNML design in 11c. The bounding box area of the proposed model is 25.65 µm2. The simulation results for the 4:1 mux design with four inputs, two select lines, and one output are shown in Fig. 12. The output of the 4:1 mux is modeled by Eq. 7. The latency for selected combinations of inputs is obtained from the simulation of the proposed layout and presented in Table 8.

$$ \begin{aligned} Y & = \overline{\overline{{M_{11} \left( \begin{gathered} 0,M_{5} \left( {1,M_{2} \left( {1,\overline{a} ,M_{1} \left( {0,\overline{s0} ,s1} \right)} \right),M4\left( {1,\overline{b} ,M3\left( {0,\overline{s0} ,\overline{s1} } \right)} \right)} \right), \hfill \\ M_{10} \left( {1,M_{7} \left( {1,\overline{c} ,M_{6} \left( {0,s0,\overline{s1} } \right)} \right),M_{9} \left( {1,\overline{d} ,M_{8} \left( {0,s0,s1} \right)} \right)} \right) \hfill \\ \end{gathered} \right)}}} \\ & = M_{11} \left( {0,M_{5} \left( {1,M_{2} \left( {1,\overline{a} ,\overline{{\overline{s0} \cdot s1}} } \right)} \right),M_{4} \left( {1,\overline{b} ,\overline{{\overline{s0} \cdot \overline{s1} }} } \right),M_{10} \left( {1,M_{7} \left( {1,\overline{c} ,\overline{{s0 \cdot \overline{s1} }} } \right),M_{9} \left( {1,\overline{d} ,\overline{s0 \cdot s1} } \right)} \right)} \right) \\ & = M_{11} \left( {0,M_{5} \left( {1,\overline{{\overline{a} + \overline{{\overline{s0} \cdot s1}} }} ,\overline{{\overline{b} + \overline{{\overline{s0} \cdot \overline{s1} }} }} } \right),M_{10} \left( {1,\overline{{\overline{c} + \overline{{s0 \cdot \overline{s1} }} }} ,\overline{{\overline{d} + \overline{s0 \cdot s1} }} } \right)} \right) \\ & = M_{11} \left( {0,M_{5} \left( {1,a \cdot \overline{s0} \cdot s1,b \cdot \overline{s0} \cdot \overline{s1} } \right),M_{10} \left( {1,c \cdot s0 \cdot \overline{s1} ,d \cdot s0 \cdot s1} \right)} \right) \\ & = M_{11} \left( {0,\overline{{a \cdot \overline{s0} \cdot s1 + b \cdot \overline{s0} \cdot \overline{s1} }} ,\overline{{c \cdot s0 \cdot \overline{s1} + d \cdot s0 \cdot s1}} } \right) \\ & = \overline{{\overline{{\left( {a \cdot \overline{s0} \cdot s1 + b \cdot \overline{s0} \cdot \overline{s1} } \right)}} \cdot \overline{{c \cdot s0 \cdot \overline{s1} + d \cdot s0 \cdot s1}} }} \\ & = a \cdot \overline{s0} \cdot s1 + b \cdot \overline{s0} \cdot \overline{s1} + c \cdot s0 \cdot \overline{s1} + d \cdot s0 \cdot s1 \\ \end{aligned} $$
(7)
Fig. 11
figure 11

The proposed 4:1 mux circuit: (a) the block diagram, (b) the pNML schematic, and (c) the pNML layout

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Table 7 The truth table of the 4-to-1 multiplexer
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Fig. 12
figure 12

The simulation results for the 4-to-1 mux using nanomagnetic pNML

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Table 8 The computational analysis of the 3D pNML layout of the 4-to-1 multiplexer
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3.7 Comparative results for the multiplexer circuits

Lots of research work based on QCA circuits is available in literature. The disadvantage of QCA technology is that it cannot operate at room temperature, whereas physical implementations of magnetic circuits are possible at room temperature [18]. Based on current research, magnetic circuits are in great demanded because they can be designed in 3D layouts and offer high speeds [19]. The mux designs proposed herein are very compact and offer low latency values. Based on the comparative analysis presented in Table 9, the new mux designs based on pNML are superior to those reported in literature [22, 31,32,33,34]. Such low-cost mux designs are appropriate for use in complex ALU and processor designs. Moreover, the proposed 2:1 and 4:1 mux circuits can be synthesized in multilayers using magnets.

Table 9 A comparison of the new multiplexer designs with literature reports
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3.8 The proposed 3D layout of the ALU

A schematic of the ALU is presented in Fig. 13a. The schematic is composed of the following modules: half adder (HA), OR, Ex-NOR, and AND gates. All the modules receive the inputs (r, s). To perform the various operations, one 2:1 mux is used. The select lines (s0 and s1) used in the mux design are involved in performing the various operations such as Ex-OR, OR, NOR, and AND. In the case of input operands rs = “01”, the selective value of mux will be fixed as s0s1 = 00 and the mux enacts the Ex-OR operation. The computational table for different input combinations of r and s is evaluated and presented in Table 10. The schematic of the ALU based on the mv gate and inverter is depicted in Fig. 13b. The complete layout of the proposed ALU is shown in Fig. 13c. The mv gates (mv12, mn13, mn15, and mn16) receive the inputs r and s and after intermediate outputs are processed by mv gates mv1 to mn10. Further, the outputs are obtained from mv11. Depending on the input r and s combination, the output node y is obtained as the final ALU output. A block-level schematic using 17 mv gates and 6 inverters is shown in Fig. 13b. The proposed layout of the ALU based on the mv and inverter gates is used to perform the various ALU operations using MagCAD tool, and the 3D layout of the proposed ALU is presented in Fig. 13c. Here in the place of inputs a, b, c, and d of the multiplexer, different logic gates are connected. The input to all the logic gates is given through p and q, which are initialized with a layer “0”, whereas the output y is taken through layer “1”. Input a is connected to the sum result of the half adder and is passed to the output line y when select lines s1 and the inverse of s0 is selected. The carry result of the half adder appears at p. Input b is connected to the OR gate and is passed to the output line when the select line is the inverse of s0 and the inverse of s1. Similarly, inputs c and d are connected to the EXNOR and AND gate, respectively. To select the EXNOR gate, the select lines are s0 and the inverse of s1, whereas to select the AND gate, the select lines are s0 and s1. The bounding box area of the proposed model is 58.59 µm2. The proposed ALU layout is simulated using ModelSim v10.4, and the simulation results are shown in Fig. 14. All the test outcomes verify the correct operation of the ALU logic circuit. Based on various input combinations, the latency value is recorded and presented in Table 10.

Fig. 13
figure 13

The proposed ALU circuit: (a) the block diagram, (b) the pNML schematic, and (c) the pNML layout

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Table 10 The computational table for the ALU
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Fig. 14
figure 14

The simulation results for the ALU using nanomagnetic pNML technology

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The model equation for the proposed ALU based on the pNML layout is

$$ y = M_{11} \left( \begin{gathered} M_{5} \left( {1,M_{2} \left( {1,\overline{a} ,M_{1} \left( {0,\overline{s0} ,s1} \right)} \right),M_{4} \left( {1,\overline{b} ,M_{3} \left( {0,\overline{s0} ,\overline{s1} } \right)} \right)} \right),0, \hfill \\ M_{10} \left( {M_{7} \left( {1,\overline{c} ,M_{6} \left( {0,s0,\overline{s1} } \right)} \right),1,M_{9} \left( {1,\overline{d} ,M_{8} \left( {0,s1.s0} \right)} \right)} \right) \hfill \\ \end{gathered} \right) $$
$$ \begin{aligned} {\mathrm{Where}}\;a & = \overline{{M_{14} \left( {1,\overline{r} s,r\overline{s} } \right)}} \\ & = \overline{{\overline{{\overline{r} s + r\overline{s} }} }} \\ & = \overline{r} s + r\overline{s} \left( {{\mathrm{Ex - OR}}\;{\mathrm{GATE}}} \right) \\ b & = \overline{{M_{15} \left( {r,1,s} \right)}} \\ & = \overline{{\overline{r + s} }} \\ & = r + s\left( {{\mathrm{OR}}\;{\mathrm{GATE}}} \right) \\ c & = M_{14} \left( {1,\overline{r} s,r\overline{s} } \right) \\ & = \overline{{\overline{r} s + r\overline{s} }} \left( {{\mathrm{Ex - NOR}}\;{\mathrm{GATE}}} \right) \\ d & = \overline{{M_{16} \left( {r,0,s} \right)}} \\ & = \overline{{\overline{r.s} }} = r.s\left( {{\mathrm{AND}}\;{\mathrm{GATE}}} \right) \\ \end{aligned} $$

3.9 Comparative results of ALU circuits

The synthesis of the custom layout is crucial for ALU circuits based on pNML technology. The compact ALU proposed herein is based on NML logic and is better in terms of latency, number of magnets or cells, and number of clocks and layers in comparison with existing literature designs. The results presented in Table 11 show that the proposed ALU design based on pNML provides a low value of latency, magnet or cell count, and clock or layer count as compared with existing designs [34,35,36,37,38]. For comparative analysis of ALUs, no designs based on pNML but more designs based on QCA are available in literature. Due to the multiple layers in the ALU design, it exhibits a better latency and number of clocks or layers than prior designs. In comparison with QCA-based ALU designs, performance parameters such as the layer count, number of magnets used, and latency are seen to be better with respect to the results presented in Refs. [34,35,36,37,38]. The newly proposed ALU shows lower cost in terms of parametric analysis, such as the layer count, magnets used, and latency. The new ALU also requires 97.13%, 93.63%, and 85.34% fewer magnets or cells in comparison with previous designs [36,37,38]. This analysis illustrates the low cost of this design compared with standard literature.

Table 11 A comparative analysis of results for ALU designs
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4 Conclusions

Various new digital circuits based on pNML technology are designed and explored herein. The introduction of the two-input Ex-OR circuit is proposed to reduce the minority-gate count in pNML-based circuits such as the parity generator, parity checker, mux, and ALU. To evaluate the newly designed digital circuit architecture, we design circuits with, e.g., Ex-OR, parity generator, parity checker, mux, and ALU functionality using the MagCAD 2.10.0 tool, extracting parameters such as the bounding box area, layer count, and latency. Simulation results based on the ModelSim v10 external simulator reveal that the latency can be reduced substantially without greatly altering the critical path, which makes the designed circuits more robust and decreases their latency for all input combinations, offering a great benefit for the design of efficient combinational circuits. A comparison of the results reveals that the proposed circuits perform better compared with state-of-the-art designs. Overall, the results presented herein represent an improvement over combinational circuits described in literature by optimizing parameters such as the bounding box area, number of clocks or layer count, and latency to make such designs robust.