1 Introduction

Nowadays, sensor-enabled devices play an important role in our daily life and are used in a wide range of applications, especially in the field of health monitoring. An important example is monitoring the ECG, since heart disease is one of the most common forms of mortality worldwide. An estimated 85.6 million American adults (more than one-third of the total population) have one or more types of cardiovascular problems [1]. Another example is to monitor respiration, which is an underestimated biosignal [2]. High RR has been observed on a large proportion of cardiac arrest patients [3, 4]. It is also helpful to diagnose pneumonia and other respiratory diseases [5]. Therefore, ECG and RR are key biosignals and the detection on both of them can significantly improve health monitoring and disease diagnosis quality.

In recent years, the design of integrated health monitoring sensors has been focused on obtaining better performance metrics (power, noise, common-mode rejection, etc.). For integrated ECG sensors, earlier versions contain resistors in the amplification stages to set the gain [6], but the performance is limited by the electrode offset as well as the mismatch and noise of these resistors. AC-coupled gain stages have been used to overcome these limitations. However, large time constants are then needed in the feedback path of the amplifier to provide the necessary corner frequencies, since the frequencies of biopotential signals are generally low (e.g., 1–150 Hz for ECG). Given the limited layout area of on-chip passive components, implementing such large time constants requires resistors that become too large when reasonable capacitor sizes (tens of pF) are assumed. A common way to address this issue is to use PMOS adaptive elements (also known as pseudo resistors) [7], and several earlier papers including our own previous work have used adaptive elements to achieve promising performance [8,9,10]. One disadvantage is the difficulty of controlling the equivalent resistance of the adaptive element, which is highly process-dependent. An alternative method to achieve high resistance is to use switched capacitors (SCs) [11]. This has the advantage that it is easy to control the equivalent resistance by changing the frequency of the clocks fed into the SCs. Clock feedthrough is a disadvantage of this approach, but this can be attenuated by fully-differential structures or additional low-pass filters (LPFs).

For RR measurements, a typical indirect detection method is to extract respiratory signals from the ECG: it is known that normal respiratory cycles amplitude-modulate the ECG [12, 13]. An alternate direct RR detection method is known as impedance pneumography (IP). Figure 1 shows the simplified model for the IP method when a four-terminal sensing system (i.e., Kelvin sensing) is used for accuracy. The thorax can be treated as two impedance components: a constant baseline impedance (\(Z_{body}+2Z_{electrode}\)) and a varying impedance (\({\varDelta } Z\)) caused by the change of chest volume during respiration [14,15,16]. Typically, \(Z_{body}\) is around \(500\,{\varOmega }\) [14], \(Z_{electrode}\) is related to the kind of electrodes used (around \(2\,\hbox {k}{\Omega }\) impedance for a standard patch electrode), and \({\varDelta } Z\) varies from 0.1 to \(1\,{\Omega }\) [15]. If a high-frequency AC current is injected into the body through the two injecting electrodes, a varying voltage is thus generated across the two sensing electrodes. Here the AC voltage behaves as a carrier signal that is amplitude-modulated by the low-frequency respiratory signal. The modulation can be extracted by a demodulator after amplification, while the carrier can be removed by low-pass filtering.

Fig. 1
figure 1

Simplified model of respiration detection by using the IP method

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Although state of the art integrated sensors have provided good performance, there is still plenty of room for further improvement. The AFE proposed here is designed to have the following advantages: (1) combine ECG detection and RR detection (IP method) on the same chip; (2) use switched capacitors as large resistors to provide large time constants that can also be easily programmed by changing the clock frequency; (3) use a driven-leg CMFB circuit to increase the common-mode rejection ratio (CMRR); (4) minimize power consumption of the system by making extensive use of subthreshold transistors; (5) use fully-differential analog signal processing to increase the CMRR; and (6) use a microcontroller to automatically program the chip (gain and clock frequency) and implement AGC loops.

The paper is organized as follows: Sect. 2 discusses AFE design and signal processing for ECG and RR detection. Section 3 presents measurement results, while Sect. 4 concludes the paper.

2 Receiver design

In this section, the receiver is presented in detail. A simplified block diagram of the integrated receiver is shown in Fig. 2(a). The typical amplitude of ECG signal varies from 0.5 to 4 mV [17]. For RR, \({\varDelta } Z\) typically varies from 0.1 to \(1\,{\Omega }\) [15]. The AHA recommends a safe injected current limit of \(10\,\upmu \hbox {A}\) [18]. In this project, the maximum injected current is \(1.6\,\upmu \hbox {A}\), which causes the maximum amplitude of RR signal to be around \(1.6\,\upmu \hbox {A}\,\times 1\,{\Omega } = 1.6\,\upmu \hbox {V}\). It should be noted that even though ECG signal amplitudes are much larger than RR, in practice the two measurements generally have comparable signal-to-noise ratio (SNR). This is because of two factors: (1) the ECG bandwidth is much larger than RR (\(\sim 150\,\hbox {Hz}\) versus \(\sim 1\,\hbox {Hz}\)), which results in more noise; and (2) low-frequency 1 / f noise from the analog front-end degrades the SNR for ECG, but not RR since the latter is modulated on a relatively high-frequency carrier. In addition, since the quantization step size, i.e., least significant bit (LSB), of a moderate-resolution (8–10 bits) low-power analog-to-digital converter (ADC) is typically 0.5–5 mV, the AFE should provide at least 20 dB gain for ECG signal and 70 dB gain for RR signal to ensure that output SNR is not degraded by the ADC’s quantization noise.

Fig. 2
figure 2

Simplified block diagram of the proposed integrated analog front-end

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To collect ECG signals, two electrodes are used to make a differential voltage measurement. Following conventional notation, we refer to these as the left arm (LA) and right arm (RA) electrodes. To collect RR signals, a four-terminal sensing system is used along with the IP method mentioned earlier. A high-frequency AC current of known amplitude is injected into the tissue through two electrodes \(\hbox {RA}_{inj}\) and \(\hbox {LA}_{inj}\). The AC current is the carrier signal that is amplitude-modulated by the low-frequency RR signal, and the differential voltage is then generated across two sensing electrodes RA and LA since \({\varDelta } Z\) changes during respiration. The modulation frequency of the AC current is set to a much larger value than the ECG frequency range of 1–150 Hz (a typical value is 9.5 kHz). This choice ensures that (1) there is little interference between ECG and modulated RR signals, and (2) the RR measurement is not affected by 1 / f noise from the analog front-end.

A low-noise preamplifier is used to amplify both the ECG and modulated RR signals. The amplifier uses a driven-ground CMFB circuit to increase the CMRR. The CMFB loop uses a fifth electrode, known as the left leg (LL), for this purpose.

After the preamplifier, LPFs are used to remove the high-frequency modulated RR signal, thus recovering the ECG. To get the RR signal, high-pass filters (HPFs) are first utilized to attenuate the ECG. A quadrature demodulator (consisting of two double-balanced mixers) is then employed to extract both the real and imaginary components of the RR signal. At the output of the demodulator, band-pass filters (BPFs) are used to remove the high-frequency carrier, thus recovering the baseband RR signal. The resulting spectra are illustrated in Fig. 3. Since the amplitude of the RR signal is small, the gain of the preamplifier is not sufficient to ensure that the signal can be digitized without adding significant quantization noise. Thus, a programmable gain stage is used to provide further amplification of the complex RR signal.

Fig. 3
figure 3

Typical spectra of the ECG, modulated RR, and baseband RR signals (1) before the HPF, (2) before the quadrature demodulator, and (3) after the demodulator

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2.1 Programmable current injector and mixer

Since the varying impedance term of the thorax \({\varDelta } Z\) is hard to predict, the SNR can be poor if the modulated RR is small, while the circuit can saturate and generate inter-modulation distortion between the ECG and RR signals if the modulated RR signal is too large. Therefore, the amplitude of AC current should be programmable. To control the injected AC current, this design uses two programmable binary-weighted 4-bit current mirrors. As Fig. 4 shows, the minimum injected current is 100 nA. By using the four switches, the injected current can vary from 100 nA to \(1.6\,\upmu \hbox {A}\) in steps of 100 nA, which is smaller than the AHA-recommended safe limit current of \(10\,\mu \hbox {A}\) [18].

Fig. 4
figure 4

Programmable current mirrors and a double-balanced mixer used for generating \(I_{AC}\). The amplitude of \(I_{AC}\) can be programmed over a 1:16 range (4 bits) by the switches \(\phi _{1}\)–\(\phi _{4}\)

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At the output of the programmable current mirrors, a passive double-balanced mixer is used. The output of the two current mirrors are connected to the RF port of the mixer, and the high frequency clock signal (nominally set to 9.5 kHz) is fed to the LO port. The outputs of the mixer are connected to the \(\hbox {RA}_{inj}\) and \(\hbox {LA}_{inj}\) electrodes. Thus, an AC current is injected into the body through the electrodes, and it is amplitude-modulated by the low-frequency RR signal.

2.2 Preamplifier

Feedforward Path The schematic of the fully-differential preamplifier is shown in Fig. 5. There are two feedforward stages in the preamplifier, and the operational transconductance amplifier (OTA) of both stages is AC coupled. The mid-band gain is set by the ratio of the capacitors in each stage. The gain of the first stage is set to 10 (20 dB) while the gain of the second stage is programmable to 10 (20 dB) or 20 (26 dB). Capacitors instead of resistors are utilized here because capacitors do not contribute noise and provide good matching compared to resistors. However, the capacitive network cannot provide DC feedback for the OTA. To overcome this issue, each stage uses SC resistors as large resistors to provide the DC path and also define the lower cut-in frequency. The standard structure of a SC has an equivalent resistance of 1 / fC, where f is the clock frequency of switches and C is the capacitor value in the SC. Since the frequencies of ECG and RR are low, a cut-in frequency of 0.1 Hz in the preamplifier may be needed, which requires a resistor of around \(200\,\hbox {G}{\varOmega }\) if a large on-chip capacitor of 10 pF is used. If the smallest available reliable on-chip capacitor of 50 fF is used in the standard SC structure, then the required clock frequency is \(1/\left( C\times R_{eq}\right) =100\) Hz, which is in the frequency band of ECG signal. Therefore, a modified SC structure that can provide higher equivalent resistance is needed. Figure 6(a) shows a SC structure that provides an equivalent resistance of 10 / fC [11]. It works in the same way as the standard SC, i.e., by moving charges into and out of capacitors during non-overlapping sampling and hold phases. But in this structure, the effective capacitances are 2.5C in the sampling phase and 0.5C in the hold phase, respectively. By using series-to-parallel charge sharing between the internal stages, the charge transfer per cycle is thus reduced by a factor of ten. Therefore, large equivalent resistances can be obtained with relatively high switching frequency and reasonable on-chip capacitors.

Fig. 5
figure 5

Schematic of the fully-differential preamplifier

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Fig. 6
figure 6

a Switched capacitor (SC) topology with the capacitor value chosen as \(C=50\,\hbox {fF}\). b Frequency response of the first-order SC HPF

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Clock for Switched Capacitor An important feature of any SC circuit is its frequency response. The SC resistor and capacitor in the feedback of each feedforward amplification stage acts as an RC HPF. Since the SC resistor is a discrete-time system, the HPF’s frequency response is periodic, and nulls exist at integer multiples of the clock frequency \(f_{SC}\). The frequency of modulated RR signals should be midway between these nulls so the minimum attenuation of the signals can be obtained from the filter, as shown in Fig. 6(b). Therefore, the frequency of the RR carrier (\(f_{RR}\)) should be set to be an odd multiple of \(f_{SC}/2\), i.e., \(f_{RR}=(2n+1)f_{SC}/2\), where \(n=0,1,2\ldots\). To achieve this, a programmable digital frequency divider is designed. An external high-frequency clock is fed to the AFE, and it is used to generate the RR carrier and SC clock. The frequencies of these two signals can be controlled by programming the on-chip frequency divider so that the condition above can be satisfied.

Driven-ground CMFB A driven-ground circuit is implemented to attenuate common-mode signals, such as power line interference. The reference electrode LL, usually placed on the leg, is connected to the output of the driven-ground circuit denoted as \(V_{cmfb}\) in Fig. 5. The common-mode signal is sensed by two OTAs in unity feedback acting as buffers. Then, the sensed common-mode signal is compared with a reference voltage, and their difference is amplified by two gain stages. The first gain stage includes two OTAs, with the one in unity feedback acting as a buffered resistor. Therefore, the gain \(G_{m1}/G_{m2}\) is set by the ratio of two bias currents \(I_{bias1}/I_{bias2}\) if both are biased in subthreshold. In order to ensure that \(G_{m2}\) works within its linear range, \(I_{bias1}\) is a programmable bias current so that the gain of this stage can be controlled (from 1 to 8 in this case). The second gain stage includes an op-amp with resistive feedback. The gain set by the ratio of the resistors is 10 (20 dB) in this case. An op-amp is used here to ensure low output impedance compared to the electrode impedance of around \(2\,\hbox {k}{\varOmega }\).

Fig. 7
figure 7

a Fully differential wide-linear-range OTA (CMFB not shown). b Differential-difference OTA used for CMFB. c Complete fully differential OTA stage

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OTA design Since the proposed AFE uses a fully-differential signal chain, a fully-differential OTA is needed. The schematic of the main OTA is shown in Fig. 7(a). This is a modified version of the wide-linear-range OTA described in [19]. Common-mode feedback (CMFB) must be added to this OTA in order to set the output common-mode voltage to a desired value. The CMFB loop senses the common-mode voltage, compares it with a suitable reference voltage, and feeds back a correcting signal. Two matched resistors (which can be SC resistors) and an OTA are commonly used to detect the common-mode voltage and compare it with a reference, respectively. However, large resistors are required to prevent loading of the main OTA and degradation of its differential voltage gain. Instead, our design uses a differential-difference operational transconductance amplifier (DD-OTA) [20] for CMFB, as shown in Fig. 7(b). This circuit does not use passive components to detect the common-mode voltage, thus ensuring that the CMFB circuit has high input impedance and does not load the main OTA. The complete fully-differential OTA including CMFB is shown in Fig. 7(c). Considering the load capacitors \(C_{1}\) and \(C_{2}\), the common-mode half circuit only sees \(C_{1}\) while the differential half circuit sees \(C_{1}+2C_{2}\) [21]. Thus, the values of \(C_{1}\) and \(C_{2}\) can be adjusted to independently set the bandwidths of the differential and common-mode paths. Negative CMFB is generated by connecting the output of the DD-OTA (\(V_{fb}\)) to the bias voltage node (\(V_{B}\)) within the main OTA. In order to minimize power consumption, all transistors are biased in the subthreshold region.

Fig. 8
figure 8

Block diagram of the proposed automatic gain control (AGC) loop

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Automatic Gain Control Loop Since the preamplifier has programmable gain, various automatic gain control (AGC) loops can be designed. A generic block diagram of such a loop is shown in Fig. 8. The differential outputs of the AFE are digitized by the ADC within a microcontroller (MCU). In one approach, the output signal amplitude is compared to a user-defined threshold, and the gain of the preamplifier is set to high-gain mode or low-gain mode accordingly by programming the AFE’s serial peripheral interface (SPI) bus. In addition, the MCU can also control the SC clock. If no clock is applied, the lower cut-in frequency of the preamplifier disappears, allowing it to amplify ultra-low frequency signals. However, the input DC level shifts because of mismatched leakage currents in the two SC resistors. Therefore, the clock should be turned on occasionally to reset the DC level. By using a MCU, a user-defined threshold can be set. Once the MCU detects that the DC level has gone beyond the threshold, the SC clock is enabled and the DC level is reset.

2.3 RR path

At the output of the preamplifier, both ECG and modulated RR signals exist. HPFs are used first to attenuate the ECG. By using double-balanced mixers, both the real and imaginary components of the low-frequency RR signal can then be extracted. As we described earlier, the amplitude of RR signal is small (\(\sim 1\,\mu \hbox {V}\) at the input). Therefore, more gain stages are needed after the demodulator for further amplifying the RR signal. The circuit shown in Fig. 9 contains three parts, including a HPF and two gain stages. The HPF is a passive CR network that uses the same SC resistor described earlier. The theoretical equivalent resistance of the SC resistor is \(200\,\hbox {G}{\Omega }\) for \(f_{SC}=2f_{RR}/19=1\,\hbox {kHz}\), resulting in a cutoff frequency of around 0.08 Hz. The first gain stage includes an op-amp, where the gain of 20 (26 dB) is set by the ratio of capacitors in the feedback loop. SC resistors are again used to set up the input DC voltages. The second gain stage is a fully-differential programmable-gain amplifier (PGA) that uses two OTAs including one in unity feedback acting as a buffered resistor. The gain of this stage is set by the ratio of two bias currents to a nominal value of 10 (20 dB). Thus, the nominal value of total gain in this path is \(20\times 10=200\) (46 dB).

Fig. 9
figure 9

Circuit used for amplifying baseband RR signals after demodulation

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3 Measurement results

The receiver was fabricated in the OnSemi \(0.5\,\upmu \hbox {m}\) CMOS process. Figure 10(a) shows a die photograph of the design, which has an active area of \(1\,\hbox {mm}\times 1\,\hbox {mm}.\) Figure 10(b) shows the test bench for the measurement, which includes an evaluation PCB for testing the chip, a commercial ECG cable to inject AC current into body and also measure biopotential signals, and a commercial MCU board (Arduino Uno) that is used to program the chip via SPI and also to implement AGC loops. The chip was powered by a single 3 V power supply and consumed \(10\,\upmu \hbox {A}\) for ECG detection and \(60\,\upmu \hbox {A}\) for RR detection. In wireless applications, it can be easily powered by two 1.5 V alkaline batteries or a single 3 V lithium battery. In addition, the area and power consumption can be easily reduced by using a more modern CMOS process that has smaller transistors, larger metal-to-metal capacitor density, and lower power supply voltage.

Fig. 10
figure 10

a Die photograph of the fabricated AFE, which has an active area of 1 mm \(\times\) 1 mm. Major blocks are labeled. b Photo of the measurement test bench. Major blocks are labeled

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Figure 11 shows measurement results on the preamplifier. Since the low-frequency corner of the preamplifier is set by the SC resistor, it can be programmed by changing the clock frequency \(f_{SC}\). Figure 11(a, b) show measured AC responses of the preamplifier with low-gain and high-gain settings, respectively. The plots show that the low-frequency corner increases with \(f_{SC}\), as expected. When no clock is applied, this pole does not exist anymore; the SC networks simply act as “off” switches that set the DC level of the preamplifier. Thus, users can easily change the low-frequency response of the preamplifier by programming the on-chip frequency divider circuit. It is convenient to either reduce the low-frequency corner to measure signals with ultra-low bandwidth, or increase it to minimize settling time and improve SNR. Besides, the mid-band gain is \(\sim \,41\,\hbox {dB}\) (high-gain mode) and \(\sim \,36\,\hbox {dB}\) (low-gain mode), which are in good agreement with simulations. Figure 11(c) shows the measured input-referred noise PSD of the preamplifier, which is dominated by 1 / f noise. The estimated minimum detectable signal is \(26\,\upmu \hbox {V}\) in the band of 1–100 Hz. Although this number is not as good as other reported works, it is sufficient for reliable ECG measurements. Figure 11(d) shows a three-lead ECG signal detected with standard patch electrodes placed on the chest (RA and LA) and leg (LL). The data has been filtered with a third-order zero-phase Butterworth LPF (\(f_c=30\,\hbox {Hz}\)). The QRS complex is easily visible in the measured data, but the P and T waves are not. This issue comes from a design miscalculation on the low-frequency corner of the preamplifier formed by the SC resistor and the capacitor in the feedback: the lower cut-in frequency is \(\sim \,4\,\hbox {Hz}\) instead of an ideal value of \(\sim \,0.5\,\hbox {Hz}\), resulting in attenuation of the low-frequency P and T waves. This issue can be easily fixed by using a larger on-chip capacitor.

Fig. 11
figure 11

a Measured AC response of the preamplifier with high-gain setting. b AC response of the preamplifier with low-gain setting. c Input-referred noise PSD of the preamplifier. d ECG signal from a male subject filtered by a third-order zero-phase Butterworth LPF (\(f_c=30\,\hbox {Hz}\))

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To measure CMRR of the preamplifier, the inputs were first connected together as a single input node, and an AC common-mode signal was applied. Figure 12(a) shows the CMRR without the driven-leg circuit. By itself, the fully-differential forward path provides a CMRR of \(41+19.4=60.4\,\hbox {dB}\). To measure the closed-loop CMRR with the driven-leg CMFB loop, a small common-mode signal was applied to the single input node of the preamplifier through a resistor \(R_{CM}\) (modeling the impedance of the interference source), and the CMFB output was connected to the same node through another resistor \(R_{CMFB}\) (modeling the impedance of the leg electrode) as shown in Fig. 12(b). These two resistors should be properly chosen to obtain a realistic estimate of CMRR. For example, the CMFB loop would not be able to attenuate the input common-mode signal if \(R_{CM}\) was too low. In our measurements, both these resistors were set to \(10\,k{\varOmega }\); this is a conservative choice since in practice \(R_{CM}\) is likely to be greater than \(R_{CMFB}\) [10]. Figure 12(c) shows the common-mode AC response at the single input node of the preamplifier with different programmable gain settings for the driven-leg circuit. The measured gain is proportional to the programming word and is also in good agreement with theoretical values. With the largest CMFB gain setting, a CMRR of 38 dB can be obtained. Therefore, the total CMRR of the preamplifier is 41 dB (high-gain mode) \(+ 19.4\,\hbox {dB}\) (fully-differential) \(+ 38\,\hbox {dB}\) (driven-leg CMFB) = 98.4 dB. Figure 12(d) shows measured transient waveforms when a large common-mode signal (a 60 Hz, 100 mV peak-to-peak voltage sinusoidal signal) was fed to the input of the amplifier. The driven-leg circuit generated an inverting signal to cancel this disturbance, as expected. Figure 12(e) shows typical measured raw ECG signals at the output of the preamplifier without any filtering when the driven-leg circuit was used and not used, respectively. Clearly, the CMFB circuit significantly attenuates common-mode noise, which allows the R peaks to be directly seen without any filtering.

Fig. 12
figure 12

a Measured open-loop common-mode AC response for the feedforward path in the preamplifier. b Closed-loop CMRR measurement setup including the driven-leg CMFB circuit. c Measured closed-loop AC response for the driven-leg circuit. d The driven-leg circuit drives the leg electrode in opposition in order to cancel a large input common-mode signal with a frequency of 60 Hz and peak-to-peak voltage of 100 mV. e Measured raw ECG at the output of the preamplifier without any filtering with and without the driven-leg circuit

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Figure 13 shows experimental results for two automatic control functions implemented in the system by using an external MCU board (Arduino Uno): (1) automatic programming of gain based on the output signal amplitude to increase dynamic range (DR), and (2) automatic turning on/off of the SC clock to reduce the lower cut-in frequency of the preamplifier and remove clock feedthrough. Figure 13(a) shows the measured transient response when the input signal amplitude is changed from 2 to 6 mV at \(\sim \,11\,\hbox {s}\) and changed back to 2 mV at \(\sim \,36\,\hbox {s}\). The AGC loop automatically changes the gain from high-gain to low-gain mode when the input signal amplitude increases, and from low-gain to high-gain mode when it decreases. Figure 13(b) shows that the DC level at the output of the preamplifier drifts with time because of the leakage current when the SC clock is turned off. Once the DC level goes beyond a user-defined threshold, the clock is automatically turned on to reset the DC level. In this case, the SC networks act like DC reset switches so that the lower cut-in frequency decreases and the preamplifier can amplify ultra-low frequency signals. In addition, the measured DC voltage drift can be fitted to a linear line with a slope of \(-\,0.004\,\hbox {V/s}\), which corresponds to a small differential leakage current of 4 fA at the input terminals of the preamplifier.

Fig. 13
figure 13

a Measured AGC results when the input signal amplitude was changed from 2 to 6 mV at 11 s and changed back to 2 mV at 36 s. Gain was set automatically by the MCU. b Another AGC function: the SC clock automatically starts to run whenever the output DC level of the preamplifier reaches a user-defined threshold, which causes it to be reset

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Figure 14 shows measured RR signals obtained by using the four-terminal sensing system and the driven-leg circuit. The volunteer held his breath during the first 4 s (background measurement), and then took fast deep breaths as shown in Fig. 14. Clear RR signals were obtained in both I and Q branches in the time domain (top and middle plots), which suggests that \({\varDelta } Z\) is not purely resistive at the measurement frequency of \(f_{RR}=9.5\,\hbox {kHz}\) (in fact, it has a significant capacitive component). The RR peak is also clearly visible in the frequency domain (bottom plot), which was found by taking the fast Fourier transform (FFT) of the complex RR signal.

Fig. 14
figure 14

Measured I and Q RR signals (top and middle) and the corresponding frequency spectrum (bottom) when the volunteer took fast deep breaths

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The volunteer had to take fast breaths (\(\sim \,2.5\,\hbox {Hz}\)) for this measurement because of a design bug in the chip: the lower cut-in frequency of the RR baseband amplifier shown in Fig. 9 was too high. Ideally the cut-in frequency should be set by the HPF, which is formed by the big capacitor (10 pF) and the SC resistor, but the first gain stage of the RR baseband amplifier in Fig. 9 currently limits the cut-in frequency. This can be easily fixed by using larger input and feedback capacitors in the first gain stage.

Fig. 15
figure 15

a Measured time and frequency-domain EMG signals generated by contractions of the biceps brachii muscle. b Measured time-domain GSR signals generated by sudden stimuli. GSR was measured between the index finger and the little finger on one hand when applying an AC stimulating current (400 nA amplitude and 20 Hz frequency)

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Table 1 Comparison table of the reported works
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The chip can also be used to measure some other important biopotential signals, including electromyogram (EMG) and galvanic skin response (GSR). Figure 15(a) shows typical EMG signals in the time and frequency domains measured using standard patch electrodes placed on the biceps brachii muscle. Individual muscle contractions are clearly visible. Figure 15(b) shows the GSR measured between the index finger and the little finger on one hand in response to sudden stimuli (self-inflicted blows to the face). GSR was measured with an AC stimulation current instead of the typical DC stimulation current. The reason an AC method was used here is that the preamplifier is AC coupled; moreover, earlier work has proven that DC and low-frequency AC stimulation result in similar GSR [26]. Our experiment used an AC stimulation current with an amplitude of 400 nA and a frequency of 20 Hz that was generated by the on-chip current injection circuit and the modulator. The measured results are similar to those obtained using DC stimulation with a bench-top source-measure unit (Keithley 2450).

Table 1 compares the performance of our receiver with other reported AFEs. Our design combines ECG with RR measurements and has low power consumption and high CMRR. Input-referred noise is higher than other work, but is adequate for ECG measurements.

4 Conclusion

An integrated switched-capacitor-based low-power fully-differential AFE for simultaneous measurement of ECG and RR is proposed. SC resistors are widely used in the AFE to generate large time constants that can also be easily programmed by changing the clock frequency. The AFE is highly programmable, allowing an external MCU to be used for creating various AGC loops. Successful detection of ECG, RR, EMG, and GSR signals prove the multi-modal functionality of the AFE. In the future, this chip can be redesigned in a more modern CMOS process to significantly reduce the power consumption and layout area.