1 Introduction

Silicon photonics is capable of solving the problem for the ever-soaring need of data transmission, enabling a high-yield, high-reliability and low-cost production [1, 2]. The usage of Si has been successfully applied as the backbone material among the devices including passive waveguides, photodetectors and modulators [3, 4]. However, making purely silicon-based light sources is still confronting challenges because of the indirect bandgap of Si. By virtue of hybrid integration through wafer bonding technique, well-functioning III–V-based lasers have been successfully integrated onto silicon substrates [5, 6]. As another candidate for achieving III–V light sources on Si, monolithic integration via heteroepitaxy could bring about lower cost and power consumption for Si-based photonic integrated circuits (PICs) [7]. Therefore, realizing high-quality heteroepitaxy of GaAs on Si should be the primary work because GaAs has been the widely used in Si-based quantum-well (QW) lasers and self-assembled quantum-dot (QD) lasers [8,9,10,11,12]. Nevertheless, crystal defects such as antiphase domains (APDs), threading dislocations (TDs) and thermal cracks will be induced during the epitaxy process of III–V/Si [13]. Such defects would serve as non-radiative recombination centers for carriers and seriously degrade laser performances. Over the past twenty years, the issues of APDs and thermal cracks have been well tackled via Si-surface pretreatment and epilayer-thickness controlling, respectively [13]. Therefore, they have been not the major problems for the room-temperature (RT) continuous-wave operation of Si-based lasers, while high-density TDs still limit the device performance, especially the QW ones [10].

To reduce the TDs forming at the GaAs/Si interface, various methods have been taken and the surface threading dislocation density (TDD) of the GaAs epilayer was successfully reduced [14]. Among these methods, InGaAs/GaAs strained-layer superlattices (SLSs) as dislocation filter layers, which drive TDs to bend towards the strained interfaces and promote the annihilation probability of TDs, have been the most common one in a molecular beam epitaxy (MBE) system [12, 15, 16]. In contrast, as an indium-free technique, thermal cycle annealing (TCA) takes advantage of the thermal expansion coefficient mismatch between GaAs and Si (αGaAs − αSi ≈ 3 × 10–6/K) to generate thermal stress for TD’s glide and annihilation. Previous studies have revealed the capacity of TCA in reducing the TDD of GaAs/Si virtual substrate in metal–organic chemical vapor deposition (MOCVD) systems. For example, in 2020, Ko et al. fabricated an MOCVD-grown GaAs/Si virtual substrate through AlAs nucleation layer and two times of TCA, showing a TDD of 5.45 × 107/cm2 within a 1.5 μm GaAs epilayer [17]. And, in 2021, Tsai et al. reported a GaAs/Si virtual substrate featuring a TDD of 2.4 × 107/cm2 with an epilayer thickness of 3.5 μm [18]. As to the MBE-grown ones, by using eight-cycle TCA, Shang et al. realized a TDD of 3.0 × 107/cm2 obtained from a 1.6 μm GaAs grown on GaP/Si (001) substrates, demonstrating the feasibility of TCA for improving the crystal quality of the GaAs epilayer in an MBE system [19]. Making thin-buffer low-TDD GaAs/Si virtual substrates can avoid the formation of thermal cracks and further contribute to the fabrication of Si-based III–V lasers. However, reviewing these works, it seems difficult to fabricate a low-TDD, i.e. ~ 106/cm2, GaAs/Si virtual substrate within a thin (< 2 μm) GaAs epilayer.

In this paper, we demonstrate a high-quality heteroepitaxy of GaAs on Si (001) substrates by a solid-source MBE (DCA-P600) system. The whole GaAs epilayer was only 1.84 μm. By using five times of TCA, the surface roughness and TDD of the GaAs epilayer was reduced to 1.74 nm (10 × 10 μm2) and 6.87 × 106/cm2, respectively. Periodic interfacial misfit dislocation (IMFD) arrays were observed at the GaAs/Si interface. The formation of these arrays is attributed to the movement of the near-interface TDs during the process of multi-time TCA. For further heteroepitaxy, these GaAs/Si virtual substrates will be used and lay a robust foundation for fabricating high-performance GaAs-based QD or QW lasers.

2 Growth and fabrication

As shown in Fig. 1, four epitaxial GaAs/Si virtual substrates were grown by MBE and marked with sample A, sample B, sample C and sample D, respectively. To suppress the formation of APDs, the used substrates were Si (001) wafers with 4° offcut towards the [110] plane [20, 21]. Before the epitaxial growth, the substrates were annealed at 1100 ℃ (measured by thermocouple) for 30 min to remove the native oxide layer. For sample A, the first epitaxial layer was started with a 27 nm GaAs nucleation layer (NL), which was grown at a temperature of 400 ℃ using a V/III ratio of 66.2. The second and third layer were 138 nm GaAs grown at a middle temperature (MT) of 560 ℃ and 275 nm GaAs grown at a high temperature (HT) of 675 ℃, respectively. The growth rate of the GaAs NL was ~ 0.021 nm/s, corresponding to one tenth of that used in MT- and HT-GaAs layers, and the applied V/III ratios for MT- and HT- GaAs were both maintained at 9.8. For sample B, the growth scheme was the same as that used in sample A except the thickness of MT- and HT-GaAs were 223 and 700 nm, respectively. Based on sample A, sample C carried out TCA twice and a 350 nm HT-GaAs was grown after the first TCA. The used TCA consisted of three repeats of thermal annealing in an As2-rich ambient, where the temperature was changed from 380 to 820 ℃ in each cycle and held for 5 min when reaching 380 ℃ and 820 ℃, respectively. For sample D, the TCA was employed five times and spaced by four 350 nm HT-GaAs layers, after the same epitaxial structure of sample A was grown. Although the spaced TCA was used five times, the total GaAs thickness of sample D was only 1.84 μm.

Fig. 1
figure 1

Diagram of the four MBE-grown GaAs/Si virtual substrates including: a three-step growth of 440 nm GaAs epilayer, b three-step growth of 950 nm GaAs epilayer, c two times of spaced TCA performed on the sample A structure, and d five times of spaced TCA performed on the sample A structure. The whole GaAs thickness of sample C and sample D are 790 nm and 1.84 μm, respectively

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3 Result and discussion

Figure 2 shows the surface morphology of the four samples characterized by atomic force microscopy (AFM). As shown in Fig. 2a, sample A shows a rugged surface with a root-mean-square (RMS) roughness of 4.70 nm within a scan area of 10 × 10 μm2. As an initial method, sample B was grown to reduce the surface roughness merely through increasing the epilayer thickness. However, the RMS roughness of sample B was increased from 4.70 to 5.22 nm, as demonstrated in Fig. 2b. Previous studies have revealed that TCA can give rise thermal stress to the GaAs epilayer grown on Si and thus improve the surface morphology by removing majority of TDs [22]. This is because a TD point can cause a localized protrusion or indentation on the GaAs surface and thus increase the surface roughness. In addition, taking multi-time TCA with GaAs spacer layers inserted in between two adjacent TCA can further improve the crystal quality [18]. Such idea was reproduced in sample C, the two times of TCA (each TCA includes three cycles and a temperature range from 380 to 820 ℃) was employed, spaced by a 350 nm HT-GaAs. As shown in Fig. 2c, the surface of sample C became much flatter than that of sample A, with a lower RMS roughness of 2.69 nm (10 × 10 μm2). It should be noted that performing TCA on sample B has no effect on reducing the surface roughness and even deteriorate the surface morphology by increasing the depth of rugged shapes. As to sample D, by virtue of five-time spaced TCA, the surface was greatly improved with a relatively low RMS roughness of 1.74 nm within a scan area of 10 × 10 μm2, which can be seen in Fig. 2d. A low-surface-roughness GaAs/Si virtual substrate could be more beneficial for growing QW-based laser structures because the unintentionally induced roughness could cause fluctuations at the QW interface and thus result in a degradation in laser performances due to the delocalized excitations [23].

Fig. 2
figure 2

AFM-measured surface morphologies of the four MBE-grown samples of a sample A, b sample B, c sample C, and d sample D. The RMS roughness values (10 × 10 μm2) of the four samples (from sample A to sample D) are 4.70, 5.22, 2.69 and 1.74 nm, respectively

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To initially evaluate the GaAs crystal quality, the aforementioned samples were tested by photoluminescence (PL) and Raman spectroscopy at RT (25 ℃). As shown in Fig. 3a, the respective peak intensity increases sequentially from sample A to sample D. And, the extracted full-width at half maximum (FWHM) values are 28.5 nm (sample A), 26.3 nm (sample B), 26.1 nm (sample C) and 22.5 nm (sample D), respectively. The reduced FWHM value is mainly attributed to the reduction of TDs in the GaAs epilayer, which indicates that sample D has the best GaAs crystal quality among these four samples.

Fig. 3
figure 3

a PL measurement and b Raman measurement results of the four MBE-grown samples at RT (25 ℃). The inset in b shows a zoom-in view of the TO peaks

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Raman measurement results are presented in Fig. 3b. The peaks located at about 290 cm−1 and 267 cm−1 represent the frequency of the longitudinal optical (LO) phonon and transverse phonon (TO), indicating the GaAs material and the crystal imperfections, such as TDs, respectively [24]. As shown in Fig. 3b, the TO peak intensity values of sample A, sample B, sample C and sample D are 0.101, 0.057, 0.053 and 0.034. respectively. Correspondingly, the FWHM values of the LO peaks are 7.8 cm−1, 7.7 cm−1, 6.0 cm−1 and 4.8 cm−1 for sample A, sample B, sample C and sample D, respectively. Therefore, it is apparent that sample D has the fewest crystal imperfections, which is accordance with the above PL result.

For further accurate characterization of TDD, a non-destructive measurement technique, electron channeling contrast imaging (ECCI), was used to observe the near-surface defects in GaAs epilayers grown on Si [17, 22, 25]. In our experiment, the four samples were all measured by ECCI using an accelerating voltage of 15 kV and a beam current of 4 nA. After adjusting the sample holder to a proper rotation angle with a slight tilt, an intersection point of the two orientations of {040} and {220} was centered. The selection of the two electron channeling pattern (ECP) lines could make all the expected dislocations visible.

As shown in Fig. 4, the distribution of TDs located near the surfaces of the three samples (sample A, sample B and sample C) were measured by ECCI. The all images were taken within the same scan area of 11.23 μm × 8.43 μm. In Fig. 4a, the TDD of sample A is measured to be 1.14 × 109/cm2. As the GaAs epilayer grows thicker, the TDD of sample B was reduced by one magnitude (from 1.14 × 109/cm2 to 2.24 × 108/cm2), as presented in Fig. 4b. Owing to the larger misfit-induced strain in the thicker GaAs epilayer, TDs tend to bend and thus cause the strain relaxation [26]. In this process, a pair of TDs who have opposite sense from Burgers vectors would move to each other and finally lead to their annihilation. For comparison, using TCA can induce more strain in the GaAs epilayer than the only usage of thicker epilayer. In Fig. 4c, compared to sample B, sample C owns a lower density of TDs which is 1.65 × 108/cm2 within a thinner GaAs epilayer.

Fig. 4
figure 4

ECCI images of a sample A, b sample B, and c sample C. The measured TDD of the three samples (from A to C) are 1.14 × 109/cm2, 2.24 × 108/cm2 and 1.65 × 108/cm2, respectively

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As discussed above, TCA can effectively reduce the surface density of TDs in a GaAs/Si sample. By using five times of TCA, the TDD of sample D was significantly reduced. As shown in Fig. 5, four different-location regions were measured to obtain a more accurate surface TDD. The TDD values of region 1, region 2, region 3 and region 4 are 8.45 × 106/cm2, 5.28 × 106/cm2, 4.23 × 106/cm2 and 9.51 × 106/cm2, respectively. Therefore, the average TDD value is 6.87 × 106/cm2. It should be noted that further-increasing TCA cycles would be not as effective as expected in reducing TDs because the glissile TDs have been annihilated by other ones or have propagated to the wafer edge after the prior five times (15 cycles) of TCA.

Fig. 5
figure 5

Four ECCI-measured images of sample D, including a region 1 with a TDD of 8.45 × 106/cm2, b region 2 with a TDD of 5.28 × 106/cm2, c region 3 with a TDD of 4.23 × 106/cm2, and d region 4 with a TDD of 9.51 × 106/cm2. The average TDD of these four regions is 6.87 × 106/cm2

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Theoretically, when the epilayer exceeds the critical thickness, amounts of misfit dislocations (MDs) will form at the interface to relax the strain. In a moderate strain (3–4%) system of GaAs/Si, a mix of 60° and 90° misfits is generated, leading to the emergence of propagating TDs and in-plane resident MDs. For comparison, a high strain (> 6%) system such as GaSb/GaAs relaxes through pure 90° MDs. According to this theory, highly periodic IMFD arrays were found at the GaSb/GaAs interface, which yields nearly complete relaxation for the epitaxy system and thus a low dislocation density for bulk GaSb [27]. In our experiment, periodic IMFD arrays were observed at the GaAs/Si interface of sample D.

To characterize the interfacial dislocation distribution of the four GaAs/Si samples, a cross-sectional transmission electron microscopy (TEM) measurement was carried out. As shown in Fig. 6a, b, there are amounts of TDs climbing up from the GaAs/Si interfaces in both sample A and sample B. While in sample C, IMFD arrays located at the interface were observed instead of a high density of near-interface TDs, as shown in Fig. 6c. And, a zoom-in view of IMFD arrays of sample C is presented in Fig. 6d. The two spacing distances are 12.3 nm and 11.9 nm, respectively. The formation of these arrays can be explained by the movement of TDs. During a TCA process, the near-interface TDs are ready to move due to the stress induced by the thermal expansion mismatch between GaAs and Si. If a pair of TDs who have Burgers vectors of 1/2[\(\overline{1}\)0\(\overline{1}\)] and 1/2[011], gliding respectively on (1\(\overline{11}\)) and (\(\overline{1}\)1\(\overline{1}\)) planes, would meet with each other and thus form an in-plane MD which has a Burgers vector of 1/2[110] on the (001) plane [28]. Thus, the lower TDD on the top GaAs surface of sample C can be attributed to the formation of these IMFD arrays during a TCA process, that is to say, the near-interface dislocations were prevented from propagating upward by being changed into in-plane resident ones.

Fig. 6
figure 6

Cross-sectional TEM images of a sample A, b sample B and c sample C. d High-resolution TEM image of sample C showing IMFD arrays at the GaAs/Si interface

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Previous studies have revealed that using post-growth annealing (PGA) can promote the formation of interfacial MDs and dramatically reduce the displaced atoms in a GaAs/Si system [29, 30], but the usage of multi-time TCA should be more effective. During one cycle of TCA, tensile and compressive strain will be additionally generated when the annealing temperature below and above the growth temperature of GaAs, respectively. Both of the thermal stresses could promote an existing TD to interact with another one and lead to TDs’ annihilation. Besides, the induced thermal stress is small in one-cycle annealing, let alone in a PGA process, so the low-temperature stage is needed to provide a re-establishment for thermal stress in the next cycle [19].

By increasing the number of times when performing TCA on a GaAs/Si sample, more near-interface dislocations will form into in-plane resident MDs. This would lead to a higher density of the IMFD arrays, i.e., a shorter spacing distance between two adjacent MDs. As shown in Fig. 7, IMFD arrays were observed at the GaAs/Si interface of sample D with a periodic spacing distance of 9.6 nm, which is closed to a theoretical value of 9.8 nm [31]. Such periodicity of IMFD arrays is due to the movement of Ga-As bonds, which keep stretching and bending to accommodate the mismatch until reaching a physical limit, and then leave behind misfit segments at the interface.

Fig. 7
figure 7

a Cross-sectional TEM image of sample D, showing periodic IMFD arrays located at the GaAs/Si interface and TDs climbing up from the interface. b High-resolution TEM image of the periodic IMFD arrays. The spacing distance between two adjacent MDs is 9.6 nm

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4 Conclusion

In conclusion, we have demonstrated a high-quality heteroepitaxy of GaAs on Si (001) substrates by MBE. By virtue of five-time spaced TCA, the crystal quality of the GaAs epilayer was significantly improved. The surface RMS roughness, measured by AFM, was reduced to 1.74 nm within a scan area of 10 × 10 μm2. As to ECCI characterization, the surface TDD was significantly reduced with a relatively low value of 6.87 × 106/cm2. Furthermore, periodic IMFD arrays were observed at the GaAs/Si interface with an MD-spacing distance of 9.6 nm. The formation of these arrays is attributed to the usage of multi-time TCA which causes near-interface TDs to form into in-plane MDs. The high-quality GaAs/Si virtual substrates will lay a robust foundation for fabricating III–V semiconductor lasers, especially QW-based ones, with enhanced performances.