1 Introduction

The metal–oxide–semiconductor (MOS) structures having nanocrystals (NCs) embedded in their oxide layer (smart non-volatile memory devices [1,2,3,4,5,6], third generation solar cells [7] and single-electron devices [8]) have received much attention as promising candidates to replace conventional polycrystalline silicon or silicon nitride non-volatile memories for future high capacity and low power consuming memory devices. In this structure, we see that there are likely traps present at the NC–matrix interface, at the Si/SiO2 interface. The NCs (Si, Ge,...), presence in tunneling layer contributes to either directly to the memory effect or affects the charge trapping dynamics of the NC’s. The NC’s charging and discharging are widely supposed to take place by direct tunneling of charge carriers from/to the free carrier reservoir in the semiconductor substrate. So, the charge emission from NCs cannot be characterized by direct tunneling but rather by a trap-assisted tunneling mechanism, with the Si/SiO2 interface states playing a key role as transfer nodes [9,10,11]. The energy distribution, the density of traps and capture kinetics of the interface and oxide traps are crucial for the future device applications. To obtain those information, deep-level transient spectroscopy (DLTS) could be used. Then, the DLTS technique is used to analysis the trap states in the semiconductors [12], and recently it has been applied in studying the semiconductor quantum dots (QD) [13]. To apply DLTS for studying MOS structures containing the nanocrystals it is necessary to obtain and analyze DLTS results on clean MOS structures (i.e., without nanocrystals). This will be enabling to separate DLTS signals coming from Si/SiO2 interface and Si nanocrystals.

In this work, we confirmed the contribution of interface traps in the DLTS response of a MOS with and without Si-NCs. This contribution is marked on series of electron traps with too tight activation energies. This quantum of electron traps, assured the thermionic transition from conduction band of poly-Si to conduction band of Si substrate in dark condition. Under illumination, we confirm the contribution of photoactive traps to better dots photo-charging, and consequently, the contribution of photo-generated charge carriers on the transport mechanisms.

2 Experimental details

The MOS structures were developed in the Sherbrooke University combining nanolithography and reactive ion etching (RIE) process. The schematic cross-sectional structure of our device discussed in this paper is shown in Fig. 1a. Over a silicon (N-type) substrate, a non-stoichiometric oxide layer SiOx = 1.5 is deposited by low pressure chemical vapor deposition (LPCVD) with two thicknesses: 5 and 10 nm (the fabrication and insulation of the oxide layer rich in silicon (SRO) is performed at CEA-LETI Grenoble). Then the layer is annealed of demixing for 3 min 30 s at 1000 °C to form silicon nanocrystals. A second annealing in oxygen at 1000 °C will be affected with a period of 5, 10 or 30 min. This annealing oxidizer allows the passivation of the nanocrystal surface. Finally, a high doped layer of polysilicon (with a doping density NpolySi = 2 × 1020 cm−3) is deposited by LPCVD on SiOx layer. The nanocrystals are formed by annealing the SRO in nitrogen environment. After the annealing, Si dots appear in thick and thin layers. The oxide is composed of silicon nanocrystals (Si-NCs) embedded in SiOx = 1.5 layer. The thick SiOx = 1.5 layer presents spherical silicon crystallites with an average size around 5 nm extracted from transmission electron microscopy (TEM) measurements (Fig. 1b). The Si-NC density is about ∼ 1.6 × 10−11 cm−2. A second annealing step in oxygen was also performed. We used e-beam lithography and dry etching to obtain the vertical structures. 200 × 200 µm2 active area detectors are finally obtained. The electrical insulation is provided by planar photosensitive resist: it was spun and then etched back by O2 plasma. Then semi-transparent contacts Cr/Au (10 nm/10 nm) were formed on the polysilicon through photolithography and lifting of a bi-layer LOR 5A/S1813. They were then used as etching masks RIE to isolate the capacitors. The substrate is used for electrical continuity. Table 1 shows the layer structures of MOS of two samples (A) and (B). Sample (A) has a 5-nm thick SiOx = 1.5 layer without Si-NCs (Reference), whereas sample (B) has a 10-nm thick SiOx = 1.5 and indicate the presence of Si-NCs within the oxide layer.

Fig. 1
figure 1

a The schematic cross-sectional of MOS silicon nanocrystal structure, b TEM micrograph of MOS structures with and without silicon nanocrystals

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Table 1 MOS structures
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The C–V and DLTS measurements were performed by a capacitance meter at a frequency of 1 MHz (model 410 C–V Plotter) with high resolution mode. To vary the filling pulse width, a pulse generator (Philips PM 5771) was used. The temperature measurement was varied in the range of 20–325 K using a closed-cycle liquid helium cryostat with a Lakeshore 330 auto-tuning temperature controller. For this system, the DLTS spectra will be made at a temperature where the locking frequency, f, was related to the emission rate by en = 2.13 f. [14]. The current–voltage (I–V) measurements were registered using a Keithley 238. To vary the wavelength and optical power, the illumination technique used consist of passing a light beam through a monochromator from a tungsten lamp through an input slit, which will allow us to vary the excitation light wavelength. Then, the beam obtained at the exit of monochromatic will be focused on the sample using a lens. The device allows illuminating the sample on the side of the active layer and the side of the transparent substrate. The emitted radiation is relatively monochromatic; its optical power is of the order of a µW.

3 Results and discussion

3.1 DLTS analysis

Figure 2a and c shows the C–V measurements observed in MOS structure; a: reference sample: without Si-NCs, b: with Si-NCs: MOS-NCs. First, we can see the total absence of hysteresis in the reference sample which means that there is no accumulated charge, so there is no Si-NCs at all the 5 nm Si0x = 1.5 layers. A clockwise hysteresis was observed for MOS-NCs, this hysteresis should be attributed to electron trapping into the Si-NCs or /and the interface of the nanocrystal dots, and not to defect in the oxide matrix or at the Si substrate/tunnel oxide interface [15].

Fig. 2
figure 2

Double sweep C–V curves and DLTS characteristics of the MOS; a and b structure without NCs, c and d devices containing NCs

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The density of traps and the information regarding the energy distribution are crucial for the future device MOS applications. To obtain this information, deep-level transient spectroscopy (DLTS) could be used [12, 13].

A DLTS measurements have been carried out in temperature range from 50 to 320 K by varying the applied gate voltage from − 2 to 0.5 V for windows (en = 426 s− 1) and a filling pulse time of 0.5 ms (Fig. 2b: reference sample, and d: the MOS-NCs).

The DLTS is a well-established technique which is commonly used in studying the trap states in the semiconductors [16], recently it has been applied in studying the semiconductor-based nanocrystals [17]. In Fig. 2b, we have observed onepositive signal for a large range temperature (120–300 K) in the DLTS spectrum for the MOS structure without Si-NCs. This signal is probably a DLTS response of a series electron traps with energy levels too close. This hypothesis can be enhanced by the DLTS response for a Si-NCs-MOS (Fig. 2d), where we can see clearly the separation on a series of multi-electron trap. Moreover, one positive signal corresponding to an electron trap has appeared for low temperature (70 K).

The principle of the DLTS technique consists in the analysis of the emission and capture assessed traps to variations in capacitance of a p–n junction or a Schottky diode. This is achieved by charging and discharging the traps repetitively, with a positive and /or negative polarization voltage applied to the sample. The curvature of the energy bands of semiconductor varied with the applied voltage, so a trap charge state will be dependent of the polarization and the capacity of the space charge region will be affected. During the pulse charging, the space charge zone decreases and the traps that lie below the Fermi level can be filled. To explain the origin physical of these signals, we need information on space zone depleted by the voltage bias, so the first step is the calculation of space charge zone extension ‘w’. In our case, we assume that the deep defect concentration is uniform with the space charge zone extension ‘w’ as the following Eq. (1) demonstrates [18]:

$$w=\sqrt {\frac{{2\varepsilon }}{{q\left( {{N_{\text{d}}}\;+\;{N_{{\text{T}}\partial }}^{+}} \right)}}\left( {{V_{{\text{bi}}}} - {V_{\text{r}}} - \frac{{kT}}{q}} \right),}$$
(1)

where \({N_{\text{d}}}\) is the doping concentration, \({N^+}_{{\text{T}}}\) is the deep defects concentration, \({V_{{\text{bi}}}}\) is the intrinsic potential, and \({V_{\text{r}}}\) is the applied potential.

Our structures are doped N+ following densities (NSi = 6 × 1017 cm− 3 and NPoly−Si = 2 × 1020 cm− 3), which give a value of ‘w’ about 238 µm, so we can assume that the totality of the structure is scanned by the potential.

At low temperature (about 70 K), we can see that the electron trap appears only for the MOS with Si-NCs, so it is likely that a silicon nanocrystal DLTS response (Si-NCs DLTS response) has a high size dispersion of quantum dots which are considered as storage nodes. The thermally stimulated process is involved in the electron capture (hole emission) in the Si-NCs. In this case, the interface state may play a key role as transfer nodes [11]. The intrinsic levels of quantum dot are present on the energy band [11, 17] which is a series of discrete energy levels [17]. Applying low electrical pulse duration induces filling of the deeper levels and DLTS peak will be near of a discrete level. Increasing this time does not affect the deep levels of response, but the response of other shallower levels is added to the DLTS signal. These levels have lower activation energies, therefore, faster emission (14 meV in our case; see Table 1; Fig. 6). This elementary reasoning explains the usefulness of a lower temperature to ensure detrapping carriers [19].

To explain the origin of the electron traps marked in Fig. 2b (The DLTS response of MOS structure without NCs), we varied the pulse duration from 0.2 to 0.5 ms, where we observed the variation of the amplitude of the DLTS peak for the same emission window (Fig. 4a).

The broad peak is a little decomposed for the low pulse duration [especially for the low time duration (0.3ms: Fig. 4a)]. As the saturation of these defects is fairly broad, this can be attributed to an extended series of electron traps behavior, having energy levels overly confined [20]. So basically, these levels are inherited in the oxide growth. Moreover, we note that the maximum of DLTS peak shifts to lower temperatures corresponding to increasing the window of issuance (Fig. 4b). A theoretical analysis and a measurement of the bulk traps and interface states in Si-MOS diodes demonstrated the distinction between interface charge and bulk traps [21]. This study confirmed that the emission rate of bulk traps at a temperature is constant regardless of the pulse bias for any pulse duration.

The peak temperature and shape of variation of transient capacitance should not change with pulse bias as time function (pulse duration), and consequently, their variation are not change. We keep the same rate window (462 s−1), and constant reverse bias − 2v but variable pulse duration (between 0.2, and 0.5 ms) on the MOS without Si-NCs. The obtained spectra are presented in Fig. 4a. In these DLTS spectra, we can see that the amplitude increasing with the pulse duration. At first, we can connect this result with the distorted in C–V curves (Fig. 3a, b). This results confirm the response of interfaces traps in DLTS analysis [15, 21]. This response is likely the emission/capture of charge carriers by an interface states and near-interface border traps [22].

Fig. 3
figure 3

Extraction of parameters \(({G_{\hbox{max} }}\) and \({C_{\text{m}}}=)\) from the Hill–Coleman method: a for MOS without Si-NCs \(({G_{{\text{max}}}}\) = 3.9 × 10− 6 S, \({C_{\text{m}}}=\) 5.5 × 10−11 F), and b for MOS with Si-NCs \(({G_{{\text{max}}}}\) = 8.3 × 10− 6 S, \({C_{\text{m}}}=\) 3.45 × 10−11 F)

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Fig. 4
figure 4

The DLTS characteristics of the MOS structure without NCs: a the DLTS amplitude depending on pulse duration time, b DLTS characteristics depending on emission window

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The density of interface traps will be calculated using a Coleman–Hill method according to the following equation [23]:

$${D_{{\text{it}}}}\;=\;\frac{{(2/qs)({G_{\hbox{max} }}/w)}}{{\left[ {{{\left( {{G_{\hbox{max} }}/w{C_{{\text{ox}}}}} \right)}^2}\;+\;{{\left( {1 - \frac{{{C_{\text{m}}}}}{{{C_{{\text{ox}}}}}}} \right)}^2}} \right]}}.$$
(2)

With q the charge of the electron, S the surface in contact between the substrate and the gate oxide and between the gate oxide and the gate, Gmax the maximum value of the conductance at the excitation frequency (see Fig. 3), and Cmax the capacitance measured on the C–V curve at the same voltage as Gmax (see Fig. 3).

This method was well detailed in the following reference [24]. In our study, we used the conductance technique to determine the surface parameters with more accuracy than capacitance technique [25], because the conductance comes only from the interface states [26]. The conductance losses are the base of conductance technique, resulting from the exchange of majority carriers between the interface states, when a small AC signal is applied to the devices [27]. To calculate the approximate maximum density of surface states for our samples, we need only to determine the maximum value of conductance (Gmax) on the G–V plot from Fig. 3a and b which involves capturing single C–V and G–V curves of the device. Once, we find the values of peak conductance on the G–V curve and the corresponding capacitance to that peak on the C–V curve, this values will be used to calculate the interface trap density of the device by Eq. (2).

The value of this last density is about 2.49 × 1012 \({\text{e}}{{\text{v}}^{ - 1}}{\text{c}}{{\text{m}}^{ - 2}}\) for a MOS structure without Si-NCs, and \({D_{{\text{it}}}}\) = 6.1 × 1012 \({\text{e}}{{\text{v}}^{ - 1}}{\text{c}}{{\text{m}}^{ - 2}}\) for a MOS-Si-NCs.

To test our hypothesis, we present the fitting of the DLTS response of NCs-MOS (Fig. 5). We assume that it is a series of multi-electron traps (five electron traps for MOS without Si-NCs, and six for a MOS having Si-NCs.

Fig. 5
figure 5

DLTS deconvolution: a MOS without Si-NCs, b with Si-NCs

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We can see also that it is the same activation energies order for the series of electron traps (with and without Si-NCs), so this is a DLTS response for same traps centers for our MOS structures. The activation energies for this series of electron traps are too close (between 0.28 and 0.45 eV for a temperature range between 120 and 300 K (Tables 2, 3; Fig. 6). These traps have strong influence on the charge transport behavior, in which the traps and defects at the internal/surface of Si-NCs and the interface states at the SiO2/Si substrate play different roles, respectively. It is suggested that the injected charges are mainly stored in the deep traps of Si-NCs instead of the conduction band in long-term retention mode [28]. The long-term charge-loss process is primarily determined by the direct tunneling of the trapped charges to the interface states in the present experiment. The deep trapping centers are assured by quantum confinement and Coulomb charge effect [28]. In our case, the transport charge process is dominantly by the thermionic fast emission/capture of the charge carriers from the highly doped poly-Si layer to the conduction band of substrate through interface traps states for a MOS structure without Si-NCs [29]. But for a Si-MOS structure, the transport process is dominated by the tunneling dot to dot of the charge carriers from the traps centers to the conduction band. The Coulomb interaction between electron and dots has sufficient time to transfer to tunnel oxide and to be captured in the NC-Si. The long-term localized charge detection characteristics in the oxidized nanocrystals can be directly attributed to their better encapsulation with SiOx = 1.5 and increased spatial isolation. This long duration time is marked in the DLTS response (a clear series of electron traps).

Fig. 6
figure 6

Arrhenius diagram: a for MOS without Si-NCs, b for MOS with Si-NCs

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Table 2 The activation energy (Ea) and capture section for MOS without a Si-NCs
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Table 3 The activation energy (Ea) and capture section for MOS with a Si-NCs
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Generally, an optimum way to improve the retention time would introduce a certain number of deep trapping centers in Si-NCs and decrease the interface states at SiO2 /Si substrate [28].

3.2 Light contribution on transport mechanisms

To analyze the light effect on the transport mechanisms, we used the I–V and C–V analyses in dark condition and under illumination.

3.2.1 I–V analysis

Figure 7 shows the current–voltage measurements of MOS having Si-NCs in dark condition and under illumination (Photo-I–V), at room temperature (Fig. 7). This last figure proved that the light effect limited only in the inversion zone. At first, we make think that is a photoactive traps effect for the voltage range comprised between (− 6 and 0 V).

Fig. 7
figure 7

I–V measurements of MOS with Si-NCs at room temperature

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Fundamentally, we recall the relationship between the Si-NCs absorbance and photon energy; this relationship is proportional to (Ephoton−Eg)2 where Ephoton is the exciting photon energy and Eg is the band gap energy [30]. This relationship confirms the Si-NCs absorbance increasing is directly related to increase the emitted energy photon increase. Moreover, we see that Si-NCs have a fast optical transition [31], so facilitate their photo-charging. In addition, the capture of photo-generated charges carriers by the Si-NCs will be better by their quantum confinement effects [32]. Based on this last arguments and on our previous works [15, 33], we can confirm, that this light effect in the inversion region is related to Si-NCs photo-charging/discharging mechanism [15] or a photoactive trap effect. This photoactive trap serves to relate the transport phenomena of photo-generated charge carriers from poly-Si layer to SiO2 through the Si-NCs.

3.3 C–V analysis

Figure 8 show the capacitance–voltage measurements in dark condition and under illumination (Photo-CV) for our MOS having Si-NCs, at low temperature (Fig. 8a), and room temperature (Fig. 8b).

Fig. 8
figure 8

C–V measurements of MOS having Si-NCs; a at low temperature, b at room temperature with the flat band evolution in time

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Figure 8 gives the evolution hysteresis phenomena with time duration of incident illumination. We can see the quasi-stable evolution of hysteresis width with the time duration. When we increase the time duration of light excitation, the hysteresis width increased also. We continue to increase the duration of light excitation, until we have saturation on the width of hysteresis after the 0.05 V/s ramp. These results can be attributed to full photo-charging of Si-NCs. The capacitance peak (~ 10 pF) appears in the inversion zone for low temperatures under photoexcitation attracts our attention. This result is directly related to the photo-generated traps effect. We can mention that this effect appeared only for low temperature. At first we recall that we have studied the traps contribution on the detection time for our devices in dark condition in our previous work [33]. The traps contribution in this last work is due to the dominance of tunneling of electrons from traps level thermally active at temperature range comprised between 240 and 280 K to the Si/SiO2 interface via the NCs-Si.

Our study confirms that is photoactive traps assured the direct exchange of photogenerated charge between Si-NCs and interface traps states [15]. Moreover, the contribution of these photoactive traps appears in the photo-detection time esteemed from the flat band evolution in time by values about 400 s (Fig. 8b). So we can conclude that Si-NCs will be better photo-charged at low temperatures through photoactive oxide traps. Consequently, the SiO2 will not behave as a dielectric, but as a metal for a high illumination [34]. This makes us think that the total capacity of the structure no more corresponds to the capacity related to the oxide [34].

4 Conclusion

The DLTS measurements demonstrate their ability to study a Si-NCs and the interface traps density contribution on the charge transport for MOS structures with a small area. We identify the trapping mechanism in the Si-NCs quantum levels through a fine potential barrier by a tunnel emission from dot to dot for low temperatures. Moreover, we have identified the response of interface traps resulting by a series of slow electron traps, especially for the low pulse duration. Moreover, the effect of photoexcitation on silicon nanocrystals photo-charging-discharging phenomena was investigated. The photo-response of MOS photo detector was related to the absorption onset shift of Si-NCs, which was affected by the photo-active oxide tunnel traps. In conclusion, our results indicate the important influence of silicon nanocrystals and the interface traps density of the charge transport for a MOS structure, and the photoactive traps contribution of transport mechanisms.