Keywords

1 Introduction

Present days the people are showing interest to do smart work to manage their regular activities without any time inconsistency. So the people are attracted by the technological circuits. People not only concentrating on the designing process they are also thinking about to do the work in fast and efficient way. To design those type of electronic systems the designers will concentrate on size of the circuit and speed and energy efficient related designs [1]. The electronic systems highly containing the arithmetic circuits to calculate the efficiency of output. Basically the summer is a main building block for the different logical blocks. These circuits are mostly utilized to transfer the data in related designs [2]. They are also used in 1/3 of power utilized microprocessors. To improve the working of the adders along with the whole design at the same time.

To design a full adder we required a few static CMOS logic models to be presented. These logics can be mainly differentiated in 2 different ways: unblended and blended model of designing. In classical model of designing process the full adder is manufactured in a unic block using transistors [3]. The terminated adder is an example of this designing model. For this circuit we are using 24 active elements to build a above and below parts of a full adder. It is generates effective fluctuating results. The main demerit that the circuit is having a large forward capacitor and is connected to a pair of N&P type transistors these can decreases the performance efficiency of the circuit. Other design for the unblended model of designing process is inverting moving transistor logic related adder [4, 5]. This circuit generates high speed and high swing output with an excellent driving capacity due to large speed multi stage, coupled transistor model and reversing at the output. It has high potential loss because of more number of inner connections in the design. We are able to design a full adder by using differential transistors [5]. The differential transistors having a demerit is that high threshold voltage drop. When the inputs are given as “10” through the pair of N&P transistors. We did not get the same output at the full adder These XOR–XNOR signals must have highly effective input and output signals.

2 Literature Survey

New technology is coming in to the VLSI designing process. As technology is changing as well as the specification designs of the system is also changing. The advanced technology is mostly concentrating on less area occupation and low power consumption and also it is concentrating on high accessing speed. These Styles are trying to have a reduced fluctuations [6, 7]. With this designing process may using 0.18 um technology and we are testing the testbench setup that measures the power consumption at full adder inputs. In this project we also concentrate on energy efficiency by reducing the size of the design. We are using different technologies to calculate the power consumption, Energy efficiency and how much area was occupied by the design of the system on chip (SOP).

In the process of working on digital signal processing we are using digital circuits like microprocessors, microcontrollers, and full adders. Which all are works on the processing the images in digital way [7]. To get the accurate designing process of a full adder we mostly concentrate on circuitry speed, area and power utilization of the circuit. To minimize the potential utility we are using different techniques like GDI design and blended transistor logic model here we are designing ripple carry adder for the wide range of applications. To design adder we are eliminating the usage of XOR/XNOR logic gates. Normally addition is the most common arithmetic operation that has to be performed using adder to design full adder we are using CMOS transistor designing process. From this paper we designed an adder by utilizing the blended CMOS logic model. It divides the entire circuit into three modules. In the first stage we can observe XOR XNOR logic circuitry [8] which generates the effective outputs and it also have good driving capacity. The second stage contains the sum circuitry which gets the input from the first stage and which produces the effective sum as output. First stage which takes the inputs from the input circuit elements which feeds its outputs to the second stage and to the third stage [9]. From the second stage we are getting sum as output and from the third stage we are getting carry as output. We proposed this hybrid CMOS multistage adder block to reduce the utilization of the potential, fluctuation between the carry input and output. In conventionally we are designing the complementary pass transistor logic (CPL) to get an effective output by reducing the transistor count [10].

3 Existing Techniques

For Fig. 1 we are giving the inputs ABC as 110, i.e., A = 1, B = 1, Cin = 0. For the XOR circuitry we are giving the inputs A&B as 11 so that both the PMOS transistors P1&P2 will become off and will generate the output as 0(zero) [10, 11]. The NMOS transistors N3 and N4 are fed with 1 and 1 so that the transistors are getting on so that the entire input is getting connected with GND so that the output becomes 0 which will store in X. The X = 0 is given as input to the N5 transistor and it becomes off, so the final output of XOR circuitry is 0, i.e., XOR = 0. For the XNOR circuit we are giving 1, 1 as input to the NMOS transistor those are N1&N2 so that the transistors are getting on it will generates the output as 1 [12, 13]. A&B is given to the PMOS transistors P3&P4 which become off so that which generates the output as 0 which output is giving as input to the transistor P5. Hence, it’s become on. The final output through the XNOR circuitry is 1 (Fig. 2).

Fig. 1
A schematic has a pair of A and B values at both ends that meet with a G N D and V D D and an XOR and an XNOR logic gate in the middle.

Existing schematic of XOR XNOR circuit

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Fig. 2
A schematic has a pair of A and B values at the top left and moves via 3 XOR and 3 XNOR gates to end in a similar structure at the left bottom.figure 2

a, b Existed conventional full adder schematic

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The author proposed a circuit of 6 T XOR XNOR logic block to design a conventional full adder. This design showed two complementary feedback boosters utilized to reuse the low performance signal in differential mode when the two inputs have unique logic. This circuit has high delay for the inputs of the same pair of logic values; outputs of this final circuit get their last voltage levels in two stages. This problem is solved by Chang. This proposed circuit generates better driving capacity, full swing at output [13]. The X-coupled diagram attaches an excess parasitic element to the XOR XNOR circuit at results. Table 1 shows the comparison table for XOR and XNOR gates at Full Swing and at partial swing. In the change method there are some defaults that are improved by Naseri and Timarchi which are designed for 12 T [14]. This circuit can take less power, produces a better delay. The XOR XNOR circuit has further changes to its better way of implementation. Even in the final circuitry we also find some mistakes when we are simulating that design by using the tanner 13 tool. In this project we are taking these drawbacks as a challenge and we are working on this project to overcome these demerits [14, 15].

Table 1 Performance of the inputs of a XOR & XNOR circuit in different paths
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4 Proposed Techniques

For the we are Fig. 3a giving the inputs ABC as 110, i.e., A = 1, B = 1, Cin = 0. For the XOR circuitry we are giving the inputs A&B as 11 so that both the PMOS transistors P1&P2 will become off and will generate the output as 0(zero). The NMOS transistors N3 and N4 are fed with 1 and 1 so that the transistors are getting on so that the entire input is getting connected with GND so that the output becomes 0 which will store in X. The X = 0 is given as input to the N5 transistor, so the final output of XOR circuitry is 0, i.e., XOR = 0 [16]. For the XNOR circuit we are giving 1, 1 as input to the NMOS transistor those are N1&N2 so that the transistors are getting on it will generates the output as 1. A&B is given to the PMOS transistors P3&P4 which become off so that which generates the output as 0 which output is giving as input to the transistor P5. Hence, it is become on. The final output through the XNOR circuitry is 1 [17].

Fig. 3
A schematic has a pair of A and B values at the top left and moves via 4 XOR and XNOR gates and a G N D and V D D to end in a similar structure at the left bottom.figure 3

a, b Proposed full adder schematic

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We are giving inputs as 110 through N8, P8 and Cin and XNOR so that the transistors become on and will generate the carry as output, i.e., Cout = 1. For the transistors P9, N9 fed with the inputs as XOR, Cin’ and XNOR so that both the transistors will become on and which will generate carry as 1. We are giving Cin, XOR and XNOR inputs as transistors P6&N6 which will turn off the transistors will generate the output as 0 that is SUM. XOR, XNOR and Cin as inputs to the transistors P7&N7 and which turns off the transistors and will generates the SUM as 0. For the design 1 we are giving the inputs ABC as 110, i.e., A = 1, B = 1, Cin = 0 [18]. For the XOR circuitry we are giving the inputs A&B as 11 so that both the PMOS transistors P1&P2 will become off and will generate the output as 0(zero). The NMOS transistors N3 and N4 are fed with 1 and 1 so that the transistors are getting on so that the entire input is getting connected with GND so that the output becomes 0 which will store in X [19,20,21]. The X = 0 is given as input to the N5 transistor, so the final output of XOR circuitry is 0, i.e., XOR = 0. For the XNOR circuit we are giving 1, 1 as input to the NMOS transistor those are N1&N2 so that the transistors are getting on it will generates the output as 1. A&B is given to the PMOS transistors P3&P4 which become off so that which generates the output as 0 which output is giving as input to the transistor P5 [21]. Hence, it’s become on. The final output through the XNOR circuitry is 1. We are feeding the XOR XNOR circuit results as inputs to the sum and carry circuitry. For the transistors P8&N8 we are giving inputs as A’, XNOR and XOR so that the transistors become on and will generates the output as 1 and for the transistors P9&N9 as Cin and XNOR and XOR so that the transistors become on will generates the output as 1. As a theoretical calculation for the input 110 we need to get carry as 1 so that we are placing the inverter at output of the carry circuit [22]. Hence, we are getting Cout as 0. For the sum circuit we are giving inputs as Cin, XNOR, XOR to the transistors P6&N6 so that the transistors become off will generates the output as 0 and Cin’ and XOR and XNOR to the transistors P7&N7 so that the transistors becomes off so that the sum circuit will generates output as 0.

5 Result

The conventional full adder proposed by the authors was scrutinized and found some drawbacks were taken as a challenge and we overcame those issues. The simulation results of the previous techniques and present techniques was represented in Table 2 for the comparison factors of Power, delay, PDP. In the older IEEE papers the authors was used the 180 nm technology and 90 nm technologies [23]. In this paper we are using 45 nm technology and we are simulating our proposed conventional full adder and we are on the inputs as ‘110’ for this input we are getting effective results. From the comparison table we plotting the graphs for voltage Vs power and Voltage Vs delay and along with Voltage Vs PDP as shown in Figs. 3 and 4.

Table 2 Comparison table for existed technology and proposed technology
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Fig. 4
Three sets of line graphs present data for voltage versus power, delay, and P D P. The graphs for power and P D P are upward oriented and the graph for the delay is downward oriented.

Proposed design graph a voltage versus power, b voltage versus delay, c voltage versus PDP

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The output plot of the proposed technology is shown in below simulated Fig. 5.

Fig. 5
Two sets of simulated outputs depict five rows of data each in the form of crests and troughs.

Simulated output results a design 1, b design 2

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6 Conclusion

In this project, a new model conventional multistage adder was established by using XOR XNOR circuit by taking reference from few of previous papers proposed by authors which generates the full swing outputs continuously. By utilizing this proposed XOR–XNOR circuit we designed 2 discrete types of adder circuits with effective outputs. The simulation results of the present XOR XNOR circuitry and the adder circuitry was verified by using mentor graphics 45 nm technology tool. The present XOR XNOR block represents decrease in words of fluctuations, Delay up to 58%, 60% and power up to 60%, PDP up to 75%, 78.02%, respectively. Then comparing with other models.