Abstract
Neural networks (NNs) are used in numerous applications such as audio–video processing and image classification. NNs can address the limitations of the traditional computer algorithms. Recently, the research utilizing field-programmable gate arrays (FPGAs) to implement NNs is on the rise due to low power dissipation, easy and fast reconfigurability offered by these platforms. This is due to the research and development efforts put into the design optimization to improve the throughput of FPGAs. The integration of appropriate hardware with advanced artificial intelligence (AI) software presents many challenges. This paper offers a generalized model of NNs on a FPGA device. In addition, it presents the design process for the high-level synthesis (HLS) tools to implement the project on FPGA. This paper shows the results of latency, timing, pre- and post-synthesis, implementation, and hardware utilization on Xilinx FPGA target device. In this paper, NN for XOR logic gate operation is performed and verified by using HLS tool, and FPGA implementation is proposed. The NN and backpropagation algorithm are developed in high-level programming languages like Python, Java, C, C++. The training part of the NN has been done by using open-source software Dev C++, and tuned weights are taken to Xilinx Vitis HLS. Simulation, synthesis, and implementation are performed by using Xilinx Vitis HLS and Vivado 2020.1 electronic design automation (EDA) tools. NN architecture with tuned weights is implemented on Xilinx ZYNQ FPGA target device. This paper shows that we were able to achieve latency in one clock cycle interval through pipeline and array partition.
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Similar content being viewed by others
References
FPGAs for Artificial Intelligence: Possibilities, Pros, and Cons. https://www.apriorit.com/ (2021)
Pan, W., Li, Z., Zhang, Y., et al.: The new hardware development trend and the challenges in data management and analysis. Data Sci. Eng. 3, 263–276 (2018). https://doi.org/10.1007/s41019-018-0072-6
Ghaffari, A., Savaria, Y.: CNN2Gate: an implementation of convolutional NNs inference on FPGAs with automated design space exploration. Electronics 9, 2200 (2020). https://doi.org/10.3390/electronics9122200
Hao, U: A General Neural Network Hardware Architecture on FPGA. CoRR abs/1711.05860 (2017)
Skhiri, R., Fresse, V., Jamont, J.P., Suffran, B., Malek, J.: From FPGA to support cloud to cloud of FPGA: state of the art. Int. J. Reconfigurable Comput. 2019, 17 (2019). Article ID 8085461. https://doi.org/10.1155/2019/8085461
Nane, R., et al.: A survey and evaluation of FPGA high-level synthesis tools. IEEE Trans. Comput. Aided Des. Integr. Circuits Syst. 35(10), 1591–1604 (2016). https://doi.org/10.1109/TCAD.2015.2513673
Korol, G., Moraes, F.G.: A FPGA parameterizable multi-layer architecture for CNNs. In: Proceedings of the 32nd Symposium on Integrated Circuits and Systems Design—SBCCI ’19 (2019)
Deotale, P.D., Dole, L.: Design of FPGA based general purpose neural network. In: International Conference on Information Communication and Embedded Systems (ICICES2014) (2014)
Quenon, A., da Silva, V.R.G.: Towards Higher-Level Synthesis and Co-design with Python. LATTE ’21, Virtual, Earth (April 15, 2021)
Novickis, R., Justs, D.J., Ozols, K., Greitāns, M.: An approach of feed-forward neural network throughput optimized implementation in FPGA. Electronics (2020)
El Moukhlis, S., Elrharras, A., Hamdoun, A.: FPGA ımplementation of artificial neural networks. IJCSI Int. J. Comput. Sci. Issues 11(2) (2014)
Ukil, A., Zurfluh, F.: Implementation of NN on Parameterized FPGA (2010)
Muthuramalingam, A., Himavathi, S., Srinivasan, E.: NN Implementation Using FPGA: Issues and Application (2007)
Rupnow, K.: A study of high-level synthesis: promises and challenges. In: 2011 9th IEEE International Conference on ASIC (2011)
Rupnow, K., Liang, Y., Li, Y., Chen, D.: A study of high-level synthesis: promises and challenges. In: 2011 9th IEEE International Conference on ASIC, pp. 1102–1105 (2011). https://doi.org/10.1109/ASICON.2011.6157401
Programming FPGAs in C/C++ with High Level Synthesis. http://people.irisa.fr/Simon.Rokicki/files/Pacap-HLS.pdf/ (2021)
Liang, Y., Rupnow, K., Li, Y., Min, D., Do, M.N., Chen, D.: High-level synthesis: productivity, performance, and software constraints. J. Electr. Comput. Eng. (2012)
Feedforward Neural Network: https://en.wikipedia.org/wiki/Feedforward_neural_network/ (2021)
Understanding Learning Rate in Machine Learning. https://www.mygreatlearning.com/blog/understanding-learning-rate-in-machine-learning/
Ghaffari, A., Savaria, Y.: CNN2Gate: an implementation of convolutional neural networks inference on FPGAs with automated design space exploration. Electronics (2020)
Gomperts, A., Ukil, A., Zurfluh, F.: Development and implementation of parameterized FPGA-based general purpose neural networks for online applications. IEEE Trans. Ind. Inf. (2011)
Understanding Backpropagation Algorithm: https://towardsdatascience.com/understanding-backpropagation-algorithm-7bb3aa2f95fd/ (2021)
Author information
Authors and Affiliations
Corresponding author
Editor information
Editors and Affiliations
Rights and permissions
Copyright information
© 2022 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.
About this paper
Cite this paper
Nagarale, S.D., Patil, B.P. (2022). RTL Verification and FPGA Implementation of Generalized Neural Networks: A High-Level Synthesis Approach. In: Shakya, S., Ntalianis, K., Kamel, K.A. (eds) Mobile Computing and Sustainable Informatics. Lecture Notes on Data Engineering and Communications Technologies, vol 126. Springer, Singapore. https://doi.org/10.1007/978-981-19-2069-1_31
Download citation
DOI: https://doi.org/10.1007/978-981-19-2069-1_31
Published:
Publisher Name: Springer, Singapore
Print ISBN: 978-981-19-2068-4
Online ISBN: 978-981-19-2069-1
eBook Packages: Intelligent Technologies and RoboticsIntelligent Technologies and Robotics (R0)