Abstract
Hardware accelerators have evolved into an important tool for meeting the ever-increasing performance demands of modern computation systems. In the modern high-performance computing domain, widely available hardware accelerators are PCIe-attached co-processors to which the host CPU can offload compute-intensive tasks. The goal of this paper is to determine whether FPGAs are a viable option as a hardware accelerator for software programmers, and if so, how their performance compares to existing processors/co-processors such as GPGPUs and CPUs in various types of HPC workloads. We can take advantage of recent advancements in high-level synthesis (HLS) tools, which enable simple programming and debugging for FPGAs. We chose OpenCL for programming because it supports a wide range of devices such as GPUs, FPGAs, DSPs, CPUs, and so on. We are using the Intel Devcloud setup for our experiments because it gives us access to modern Intel FPGAs, which can be used as hardware accelerators in conjunction with other resources such as GPGPUs and multicore processors.
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Mishra, A., Ajith, K.J., Bhatt, K., Vaibhav, K., Duggal, V. (2022). Assessing the Performance and Suitability of FPGAs as Hardware Accelerator for Software Programmers. In: Rout, R.R., Ghosh, S.K., Jana, P.K., Tripathy, A.K., Sahoo, J.P., Li, KC. (eds) Advances in Distributed Computing and Machine Learning. Lecture Notes in Networks and Systems, vol 427. Springer, Singapore. https://doi.org/10.1007/978-981-19-1018-0_44
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