Abstract
Modern computer architects can integrate an increasing number of cores on chip with the advances of chip manufacturing technologies. Manycore processors widely use network-on-chip (NoC) for providing communication between cores. In this paper, we discuss the limitations and challenges of traditional interconnects. These limitations are overcome in network-on-chip architecture. We briefly discuss the basic building blocks of NoC that are used popularly in commercial architectures. The NoC design metrics, which are the assessment parameter of NoC efficiency, are also examined in depth, and it is challenging to achieve a good trade-off in these design metrics.
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Passas, G., Katevenis, M., Pnevmatikatos, D.: Crossbar NoCs Are Scalable Beyond 100 Nodes. IEEE Transactions on Computer–Aided Design of Integrated Circuits and Systems, 31(4), pp. 573–585 (2012).
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Yadav, S. (2022). Interconnect Paradigm Shift Towards Networks-on-Chip in Manycore Processors: A Review on Challenges. In: Kumar, R., Ahn, C.W., Sharma, T.K., Verma, O.P., Agarwal, A. (eds) Soft Computing: Theories and Applications. Lecture Notes in Networks and Systems, vol 425. Springer, Singapore. https://doi.org/10.1007/978-981-19-0707-4_62
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DOI: https://doi.org/10.1007/978-981-19-0707-4_62
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