Abstract
At the advanced stage of technologies, when feature size is being reduced, it is compulsory to introduce other parameters for more accurate modelling of transmission line interconnects. So mutual inductance and coupling capacitance how have become more important role for analysis of high-speed on-line VLSI interconnects. This paper introduces a mathematical aware analysis result for crosstalk noise of ‘L’ type RLC interconnections using mutual inductance. Two RLC interconnect lines of ‘L’ type, are equidistant to each other and used as ‘Aggressor line’ and ‘Victim line’ respectively, whereas, a step signal voltage is employed as input to aggressor line. Other calculative results for Delay and peak noise voltage between these two RLC electrical lines with using mutual inductance, are also introduced in this paper. This paper also shows a comparative result between our derived expression values and BKM values for simulation purpose.
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1 Introduction
Presently, VLSI is the present level of designing and fabrication of ICs and microchips which consist of lacs of transistors on a single chip [1, 2]. In DSM region [3], now it is considered to study of inductive effect as well as capacitive-coupling effects to develop and explain the more accurate and real behaviour of on-chip VLSI interconnects. Delay and Crosstalk noise between VLSI high speed interconnected networks can have occurred due to self and mutual inductance. There are so many approaches presented [4,5,6,7,8,9,10,11,12,13,14,15,16,17,18] for the modelling of interconnect structures. This paper introduces use of closed loop of ‘L’ type RLC interconnect network. Two RLC parallel interconnects and a mutual inductance and coupling capacitance are occurred automatically. These two RLC networks are named as ‘aggressor line’ and ‘victim line’ respectively. The proposed work is much improved work of the BKM [19] model. This paper establishes a mathematical equation of crosstalk voltage of mutually inductively coupled interconnections of RLC type. This paper also introduces expressions for delay and peak noise voltage between adjacent RLC network. This paper is organized remaining follows: Sect. 2 describes Proposed models and of crosstalk voltage and delay analysis. Detailed results of simulation are discussed in portion 3 and portion 4 conclude the paper.
2 Proposed Model
Mathematical and analytical expressions for the crosstalk voltage, delay and peak crosstalk voltage are derived in the case only when victim lines are grounded and excitation is connected to aggressor line. Figure 1 shows lumped RLC model of ‘L’ shaped interconnection system considering Mutual Inductance coupling between the parallel lines. Step input voltage is used for the analysis of the interconnection system.
A step input voltage supply is given to the input of aggressor line which is equidistant to the victim lines. Coupling capacitance is generated because those two RLC networks are proximate to each other and mutual inductance is induced due to using inductor coil.in this paper we use 90 nm technology.
As per Moore’s law, in the process of designing the ICs, the number of transistors will continue to double in every 18 months [1]. That means the same silicon area would accommodate a greater number of transistors. Transistors size is gradually getting reduced for achieving this or we can say that transistor size is shifting from one technology node to smaller technology node by using scaling process. A specific technology gets used by the industries for the period of time till the time when the next feasible smaller technology node would be ready for implantation. For example, 180 nm technology was used mostly in 1999–2000-time period whereas 90 nm technology was used in 2004–2005. The technology’s numbers represent the minimum feature size of transistor or CMOS. Minimum channel length that can be used in fabrication of CMOS or transistor is known as Feature size of transistor. These numbers are decided by dividing the previous number (technology) by square root of two (\(\sqrt{2}\)).
In the circuit shown in Fig. 1, at node C, we develop the mathematical expression for the voltage for RLC victim line.
On employing KVL in 1st loop:
On taking Laplace,
Where,
Similarly, on applying KVL in 2nd mesh,
Similarly, on applying KVL in 3rd mesh,
Where
From Eqs. (3), (5) and (6), we get a matrix:
Let,
Then required matrix is,
After solving by Cramer’s rule [20],
Now, at node ‘C’:
So,
Where,
\(P = - sABCC_{1} C_{1}^{^{\prime}} - 2s^{2} mC_{1} C_{1}^{^{\prime}} + Bs^{5} m^{2} C_{1}^{2} C_{1}^{^{\prime}2} + AC_{1} + CC_{1}\) After substituting the values of A, B and C:
Where,
Where,
Now,
After neglecting all high-power terms:
Now after substituting the value of \({V}_{s1}=\frac{1}{s}\) (for step input voltage) & P in Eq. (11),
Now, let us assume:
If, \(R={\left[\sqrt{\frac{-Z}{X}-\frac{{Y}^{2}}{4{X}^{2}}}\right]}^{2}\)
After taking Inverse Laplace transform:
Peak time value \({t}_{{p}_{c}}\) is calculated by equating first derivative of \({V}_{c}\left(t\right)\) to zero,
After simplification we get
Let’s put the value t = \({t}_{{p}_{c}}\) in Eq. (14) so that,
Now calculate the value of \({V}_{B}\):
For unit step input, \({V}_{s1}=\frac{1}{s}:\)
Now let’s put the value of P from expression (12) and have,
Where,
Putting the result of P in the equation of VB1 from Eq. (13)
after simplification, we get,
In similar way, the expressions of VB2 and VB3 after substituting the expression of P from Eq. (13),
Where,
substituting the values of \({V}_{B1},{V}_{B2},{V}_{B3}\) in Eq. (17)
After using inverse Laplace Transform in the above expression
On differentiating with respect to t
Peak time value is calculated by equating first derivative to zero,
Let us assume for simplicity,
After simplification above equation becomes,
After simplification and approximation to lower degree terms of above Eq. (19), we get
where,
After substituting the values of \({t}_{p}\) in equation, so now
The expressions for peak delay time and peak voltages at node C and B are discussed by Eqs. (15), (16), (20) and (21) respectively. The essential proposed crosstalk voltage and peak crosstalk noise voltage respectively at node C are discussed by Eqs. (14) and (16).
3 Simulation Result and Discussion
Figure-1 shows simulation set-up of two L type High speed RLC mutually coupled interconnection system having 1000 μm of length. High performance CPU system designs typically consist of such type of bus structures. Symmetrical Step signal having finite and equal rise/fall time of 10 ps is used to excite the aggressor line. It is assumed that the interconnection system is identical and symmetrically distributed by considering that the system is connected with identical size of inverters for drivers and loads. Variations in the input slew times values up to 200 ps are used for the simulation of Mutually coupled interconnection system connected with identical driver size.
For the testing and verification purpose, we have compared our proposed model values with BKM [19] model values to show the novelty of our proposed work. This comparison was done on the same set of circuit parameters. Our work is much-improved version of BKM model [19] for the same L-interconnect model with the consideration of mutual inductance for high operating frequencies. Comparison of simulated results at node C for the expression given by Eq. (16) for proposed model and BKM model are demonstrated in Table 1 for various input slew times. Table 2 discusses the comparison of aggressor line voltage described by Eq. (21) with BKM model values and our proposed model for the various input slew values. Comparative results for the peak times tpc and tpb at node C and node B of the victim line and aggressor line described by Eqs. (15) and (20) respectively is discussed in Table 3 and Table 4. Comparative results for proposed model Aggressor voltage, BKM and SPICE for different values of Ts are shown in Figs. 2, 3 and 4 respectively. Similarly, comparative results for aggressor line voltage, victim line peak time and aggressor line peak time values from proposed model and the values from SPICE simulations are shown in Figs. 5, 6, 7, 8, 9, 10, 11, 12 and 13 respectively.
.
After analysing the simulated result related Figs. 2, 3, 4, 5, 6, 7, 8, 9 and 10 and Tables 1, 2, 3 and 4, we can easily find out the novelty and importance of our proposed model in comparison to BKM [19] model. By considering mutual inductance in between two coupled interconnection models, our proposed model becomes more realistic and generic as it follows SPICE results better than BKM model. Deviation in between BKM model values with SPICE values is very large therefore; BKM model becomes appropriate in current scenario.
4 Conclusion
Proposed research work discussed about the mathematical analysis of delay and crosstalk voltage in mutually coupled RLC VLSI interconnection structures. The derived models for crosstalk voltage and delay are found precise as simulation results are very close to SPICE. The L-type RLC mutually coupled interconnection system is proposed in this research work. The correctness and validity of the research work is demonstrated by the simulation results. Simulation results shows that the proposed models are having less than 10% error comparable to the results obtained from the SPICE.
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Gupta, A., Maheshwari, V., Malipatil, S., Kar, R. (2021). Delay and Crosstalk Aware Analysis for High Speed On-Chip Global RLC VLSI Interconnects. In: Nath, V., Mandal, J.K. (eds) Proceeding of Fifth International Conference on Microelectronics, Computing and Communication Systems. Lecture Notes in Electrical Engineering, vol 748. Springer, Singapore. https://doi.org/10.1007/978-981-16-0275-7_66
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