Analog and Radio-Frequency Performance of Hetero-Gate-Dielectric FD SOI MOSFET in Re-S/D Technology

Abstract

Fully depleted silicon-on-insulator (FD SOI) technology has already been accepted for its short-channel immunity in nanoscale regime and the concept of metal-gate engineering has provided the flexibility to further scale-down the device dimensions. This paper presents the analog and radio-frequency behavior of hetero-gate-dielectric (HGD) triple-metal-gate (TMG) recessed-source/drain (Re-S/D) FD SOI MOSFET at 45-nm-technology node. Here, the analog performance has been investigated on the basis of numerical calculations of transconductance (g_m), output conductance (g_d), transconductance generation factor (TGF), and intrinsic gain (A_v). Further, radio-frequency performance has been monitored by analyzing parasitic capacitances (C_gs and C_gd) and cutoff frequency (f_T). All these studies have been performed using technology computer-aided design (TCAD) simulation tool Silvaco ATLAS. It is found that the proposed hetero-gate-dielectric-based TMG SOI MOSFET exhibits excellent transconductance behavior with higher gain and increased frequency of operation as compared to other state-of-the-art discussed in the literature. The proposed device offers cutoff frequency of 5.21 × 10¹¹ Hz, which itself dictates the device immunity at high frequency. Simultaneously, the perspective of buried-oxide (BOX) thickness variation on the performance of HGD-TMG SOI MOSFET has also been investigated in order to tackle the challenges involved in nanoscale device design.

1 Introduction

The recent advancement in complementary metal–oxide–semiconductor (CMOS) technology has provided the flexibility to accommodate billions of MOS transistors in an integrated circuit (IC). These high-density ICs led to the development of high-performance and low-power circuit and systems for analog/radio-frequency applications [1, 2]. However, the backbone of these high-speed ICs is metal–oxide–semiconductor field-effect transistors (MOSFETs) [3]. So, it is the prime requirement that the available nanoscale MOS technology should offer necessary and optimized performance for the design of such high-performance ICs. However, the endless scaling of MOS transistors beyond 100 nm is continuously deteriorating the device performance and results in various short-channel effects (SCEs), like drain-induced barrier-lowering (DIBL), threshold voltage roll-off, surface-scattering, mobility degradation. [3, 4]. These adverse effects are the main cause of off-state leakage and reduced circuit performance in high-density ICs.

Recently, various solutions have been proposed in standard literatures to off-flow these leakages in nano-scaled MOSFETs. The resulting technologies like FinFET [5], junctionless transistor (JLT) [6] and FD SOI [7] have been accepted worldwide due to their excellent immunity over short-dimensional effects. Also, various techniques like metal-gate-engineering [8], multi-gate (double-gate/gate-all-around) [9], hetero-gate-dielectric (HGD) [10] have further enhanced the device performance depending upon the requirements. As FinFETs offer better analog and radio-frequency performance. However, it results in disadvantageous due to complex structures.

Moreover, as per the industrial perspective and market demand, FD SOI technology has been attracting attention for low-power and high-performance constraints and having planer structure as compared to other technologies like FinFET [11,12,13,14,15]. Also, the analyzed channel density issues are almost overcome by the use of un-doped channel techniques in FD SOI MOSFETs. Young [11] has provided the very first mathematical analysis of FD SOI MOSFETs, and Suzuki et al. [12] have optimized the buried-oxide (BOX) thickness effects by proposing analytical model. Cheng et al. [13] have reviewed the features of FD SOI MOSFETs and recommended the back-biasing technique for improved radio-frequency performance. In continuation, the proposed source engineering technique in FD SOI MOSFET overcomes the parasitic effects [14, 15].

Metal-gate engineering in FD SOI MOSFETs has also been accepted to further reduce the threshold-voltage roll-off. Kumar et al. [16] have chosen the technique of dual-material-gate to excel in the performance of FD SOI MOSFETs by optimizing step-like potential profile. In next, Srivastava et al. [17] have utilized the concept of dual-metal-insulated gate in FD SOI technology along with the source engineering and analyzed the oscillation frequency of the designed ring oscillator circuit. Maity et al. [18] have discussed the impact of buried-oxide thickness on analog/RF and circuit performance in the design of FD SOI MOSFETs. However, due to the lesser thickness of source/drain regions, the nano-scaled thin-body FD SOI MOSFETs suffers from higher series resistance [19, 20]. Moreover, the suggested recessed-source/drain (Re-S/D) technology in FD SOI MOSFETs could be analyzed to reduce this resistance. Zhang et al. [19] had proposed the design of Re-S/D MOSFET and discussed its features. In continuation, the analytical model of this approach has been given by Sivilicic et al. [20]. Also, the metal-gate engineering has been utilized further to enhance the performance of Re-S/D MOSFETs [21]. Priya et al. [21, 22] had extensively analyzed the performance of multi-metal-gate FD SOI MOSFET in Re-S/D technology and also discussed the circuit-level performance. However, the scope and advantages of hetero-gate-dielectric (HGD) technique in the design of Re-S/D technology-based triple-metal-gate (TMG) FD SOI MOSFET have not been discussed yet.

In this contribution, the analog and radio-frequency performance of hetero-gate-dielectric-based TMG FD SOI MOSFET in Re-S/D technology has been analyzed for the first time. It has been assured that the studied HGD-TMG Re-S/D FD SOI MOSFET exhibits enhanced electric performance and could be suggested for analog and radio-frequency-based communication systems. This paper has been organized into five major sections. Section 2 discusses the device structure and specification used in the design of proposed SOI MOSFET, and the fabrication feasibility of the studied MOSFET is described in Sec. 3. Then, the TCAD simulation strategies have been explained in Sec. 4. The analog and radio-frequency performance of the device are analyzed in Sec. 5. Finally, the overall work is being concluded in Sec. 6.

2 Device Structure and Description

The proposed HGD-TMG Re-S/D FD SOI MOSFET is shown in Fig. 1, and the complete device dimensions and specifications are mentioned in Table 1. The device is designed to operate at 45-nm-technology node such that all the three-metal-gates are of equal gate length (L₁ = L₂ =  L₃ = 15 nm). The front and buried-oxide thickness is termed as T_ox and T_BOX, respectively, and the thickness of silicon film is T_Si. The extension of S/D depth is called as recessed-source/drain thickness (T_rsd), and the incremented thickness of overlapped S/D region at buried-oxide interface is named as D_BOX. This extension of S/D depth assures the effective reduction in series resistance as compared to other ultra-thin body FD SOI devices.

Fig. 1

Device structure of hetero-gate-dielectric triple-metal-gate Re-S/D FD SOI MOSFET

Table 1 Device design parameters and their specifications

In proposed MOSFET, all three-metal-gates L₁, L_2, and L₃ are arranged form source-to-drain with materials aurum, molybdenum, and titanium with work functions 4.8 eV, 4.6 eV, and 4.4 eV, respectively. These metal gates are placed in such a manner that the material gate with higher work function is at source and lower work function metal is nearer to drain channel end. The metal gate with higher work function helps to off-flow the leakages in sub-threshold region, which results in increased gate controllability, so seen as control gate, whereas lower work function metal screens-off the changes at higher drain bias, so seen as screen gate.

Next, the hetero-gate-dielectric is featured with two different gate-oxide materials in symmetrical manner, such that the first HfO₂ (ε_r =  32) and second gate-oxide materials Si₃N₄ (ε_r = 7.8) are arranged form source-to-drain, respectively, as shown in Fig. 1. The hetero-gate-dielectric offers noticeable enhancement in short-channel performance as compared to single-gate-dielectric. In Table 1, the provided doping levels are used to examine the device characteristics, where source/drain doping is represented as N_S/D and the channel/substrate doping as P_Ch/Sub.

3 Fabrication Feasibility of HGD-TMG Re-S/D FD SOI MOSFET

The FD SOI MOSFETs are experimentally feasible with reduced fabrication complexity as compared to FinFETs [23, 24]. Also, the process flow of triple-metal-gate re-S/D FD SOI MOSFET is already been discussed in our previous work [22]. However, the growth of hetero-gate-dielectric in the design of TMG Re-S/D FD SOI transistor could be targeted as discussed in [24], in which, the growth of hetero-gate-dielectric is described in detail and suggested using HV vapor method to properly etch the first deposited low-k dielectric then atomic layer deposition (ALD) to form high-k dielectric. Moreover, other fabrication steps remain the same as discussed in [22], like Si-wafer pattering, oxidation of BOX layer, SOI-layer deposition, Re-S/D formation, channel growth, oxide growth, S/D implantation, contact formation with proper etching.

4 Simulation Setup

The studied hetero-gate-dielectric-based FD SOI MOSFET has been designed and simulated using technology computer-aided design simulation tool Silvaco ATLAS [25]. Various simulation models have been used for the precise analysis of the studied device. As, for the analysis of majority carrier lifetime, recombination, and Shockley–Read–Hall model is taken into considerations. Similarly, Lombardi mobility and constant voltage, and temperature model are taken for the study of mobility variations due to temperature. Gummel–Newton along with drift-diffusion model is used to analyze the on–off switching of the device. Next, to effectively monitor the impact of transversal electric on-current conduction, field-dependant mobility model is chosen [25]. Also, the investigation of the quantum confinement effect is necessary below 50-nm-technology node. For this, Bohm quantum potential (BQP) model and quantum mechanical effect (QME) model have been used during TCAD simulations.

5 Performance Analysis of HGD-TMG Re-S/D FD SOI MOSFET

This section dictates the analog and radio-frequency performance of proposed FD SOI MOSFET on the basis of numerical simulations. The comparison of drain current characteristics of proposed FD SOI MOSFET with existing state of the art [21] at 45-nm-technology node is shown in Fig. 2. It is clear from the plot that the proposed HGD-based device offers lesser off-state-leakage current (I_off) and attains higher on-current (I_on) as compared to [21]. The proposed MOSFET and referenced devices show I_off = 1.47 × 10⁻¹³ A and 7.5 × 10⁻¹² A and I_on = 2.56 mA and 1.12 mA, respectively. That results in switching ratio (I_on/I_off) of 10¹⁰ and 10⁹ for proposed and referenced device [21], respectively.

Fig. 2

Comparison of I_d versus V_gs characteristics of proposed HGD-TMG MOSFET at T_BOX = 50 nm with referenced FD SOI MOSFET [21] at V_ds = 1 V

This increment in switching performance of proposed MOSFET is due to the use of hetero-gate-dielectric in place of single-gate-dielectric. As due to the inclusion of HGD, the effective electric-field under first gate-metal will get enhanced and that gives rise in gate control over device channel. Also, triple-metal-gate structure will provide step-like potential profile, which helps to reduce electric field penetrations due to applied drain voltage in short-dimensional MOSFET. This will further reduce drain-induced barrier-lowering effect.

5.1 Analog Performance of Studied FD SOI MOSFET

In this section, the analog performance of the studied FD SOI MOSFET has been monitored on the basis of numerical calculations of transconductance ($g_{m} = \partial I_{d} /\partial V_{gs}$), output conductance ($g_{d} = \partial I_{d} /\partial V_{ds}$), transconductance generation factor (TGF = $g_{m} /I_{d}$), and intrinsic gain (A_v = $g_{m} /g_{d}$).

The plot of transconductance as a function of gate voltage at different buried-oxide thickness is shown in Fig. 3 at V_ds= 1 V. The transconductance examines the carrier transport efficiency of the device, and it should be high for higher gain. It is depicted in Fig. 3 that the proposed HGD-based device excels the device transconductance and offers g_m of 4.38 mS, 3.72 mS and 3.45 mS at T_BOX = 50 nm, 75 nm, and 100 nm, respectively, with lower voltage of operation, and this leads to an improved performance when used with low-power analog circuits.

Fig. 3

Analysis of transconductance behavior versus gate voltage of proposed HGD-TMG MOSFET at T_BOX = 50–100 nm

Also, the analysis of transconductance generation factor (TGF) at different T_BOX is shown in Fig. 4. The TGF investigates the effectiveness of transconductance toward the current conduction with thermal stability. One can get from Fig. 4 that the studied device offers reduction in TGF value with applied gate bias and better performance at T_BOX = 50 nm. This is needed for proper operation of highly linear analog ICs.

Fig. 4

Plot of transconductance generation factor (TGF) versus gate voltage with variation in T_BOX at V_ds = 1 V for proposed HGD-TMG MOSFET

Similarly, output conductance behavior of the studied SOI MOSFET is plotted in Fig. 5. The output conductance must be as low as possible for higher gain in analog devices and circuits. The studied device exhibits lower output conductance at T_BOX = 50 nm and L  = 45 nm. So, the studied MOSFET could be optimized at T_BOX = 50 nm for better analog performance. Now, the analyzed intrinsic gain (A_v) of HGD-based SOI MOSFET is shown in Fig. 6. It is found from the plot that the device exhibits better intrinsic gain at optimized T_BOX and L  = 45 nm.

Fig. 5

Analysis of output conductance with applied drain bias at different T_BOX for proposed FD SOI MOSFET

Fig. 6

Calculated intrinsic gain (A_v) of proposed FD SOI MOSFET at different T_BOX

5.2 RF Performance Assessment

For better RF characteristics, the device should attain excellent parasitic behavior along with higher cutoff frequency. Here, the radio-frequency performance has been investigated on the basis of TCAD numerical simulations. Firstly, the AC simulations have been performed to calculate the gate-to-source and gate-to-drain parasitic capacitances (C_gs and C_gd). The plot C_gs with variation in gate voltage is shown in Fig. 7. It is found that the studied device offers lesser value of parasitic capacitance at higher T_BOX and also considerable performance at lower T_BOX. This is due to the effective suppression of trans-capacitances due to the inclusion of HGD technique in SOI MOSFETs. Similarly, plot of C_gd at different T_BOX is presented in Fig. 8, which also dictates the immunity of the studied device at 45 nm node. The device presents C_gs = 0.639 fF and C_gd= 0.230 fF at T_BOX = 100 nm and L  = 45 nm.

Fig. 7

Plot of gate-to-source parasitic capacitance (C_gs) versus gate voltage at T_BOX = 50–100 nm and V_ds = 1 V for proposed MOSFET

Fig. 8

Plot of gate-to-drain parasitic capacitance (C_gd) versus gate voltage at T_BOX = 50–100nm and V_ds = 1 V for proposed MOSFET

Next the analysis of cutoff frequency $\left(f_{T} = g_{m} /2\pi \left( {C_{gs} + C_{gd} } \right)\right)$ is taken into consideration. The higher cutoff frequency is desired for the investigation of allowable bandwidth in radio-frequency integrated circuits (RFICs) communication systems. Figure 9 represents the plot of cutoff frequency with variation in gate voltage at different T_BOX. The device exhibits very close results at T_BOX ranging from 50 to 100 nm. However, the device offers better RF behavior at higher T_BOX and better transconductance at lower T_BOX. So, this leads to almost constant cutoff frequency for T_BOX range from 50 to 100 nm. The proposed hetero-gate-dielectric SOI MOSFET offers f_T = 5.21 × 10¹¹ Hz at T_BOX = 50 nm and L  = 45 nm.

Fig. 9

Analysis of cutoff frequency at T_BOX = 50–100 nm and V_ds = 1 V for proposed MOSFET

Table 2 presents the exact analysis of analog and radio-frequency performance parameters of hetero-gate-dielectric TMG Re-S/D FD SOI MOSFET. One can depict that the studied device is having better analog/RF performance. So, as per the above-discussion, it is clear that the utilization of hetero-gate-dielectric is advantageous in the design of triple-metal-gate Re-S/D FD SOI MOSFET. Also, the analysis over buried-oxide thickness provides the tradeoff to optimize the T_BOX according to the requirements in electronics circuit and systems. This type of performance itself dictates that the proposed device could be an alternative in RFICs-based communication systems.

Table 2 Analog and radio-frequency parameters of proposed HGD-based SOI MOSFET at different T_BOX for L = 45 nm

6 Conclusion

This work presents the perspective of hetero-gate-dielectric technique on analog and radio-frequency performance of HGD-TMG Re-S/D SOI MOSFET. It is assured that the studied MOSFET exhibits significant features at 45-nm-technology node for low-power analog/RF applications. The proposed device exhibits off-state leakage of I_off = 1.47 × 10⁻¹³ A and on-current I_on = 2.56 mA at T_BOX = 50 nm, L  = 45 nm, and V_ds = 1 V. This results in switching ratio I_on/I_off = 10¹⁰, which is sufficient to reduce the leakage issues in off-state. So, it is advantageous to use the HGD technique in Re-S/D technology-based FD SOI MOSFET. This leads to a motivation to further investigate the device performance for analog/RF applications. Here, the analyzed results present a noticeable enhancement in transconductance behavior (g_m = 4.38 mS) with higher gain of 32.68 dB at optimized dimensions. Also, the device shows better g_m/I_d value of 33.61 V⁻¹ in weak-inversion region, which is good for thermal stability of highly linear analog ICs. Further, the device shows a better parasitic immunity with C_gs and C_gd in order of femto-farads and the cutoff frequency of the device is found as f_T = 5.21 × 10¹¹ Hz. Hence, the HGD-based SOI MOSFET could be suggested for the design of low-power analog ICs in radio-frequency-based communication systems.